2 * Copyright (c) 2011, Google Inc. All rights reserved.
3 * See file CREDITS for list of people who contributed to this
5 * Portions Copyright 2011-2012 NVIDIA Corporation
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef _TEGRA20_GPIO_H_
24 #define _TEGRA20_GPIO_H_
27 * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
30 #define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
31 #define TEGRA_GPIO_BANKS 7 /* number of banks */
33 #include <asm/arch-tegra/gpio.h>
35 /* GPIO Controller registers for a single bank */
36 struct gpio_ctlr_bank {
37 uint gpio_config[TEGRA_GPIO_PORTS];
38 uint gpio_dir_out[TEGRA_GPIO_PORTS];
39 uint gpio_out[TEGRA_GPIO_PORTS];
40 uint gpio_in[TEGRA_GPIO_PORTS];
41 uint gpio_int_status[TEGRA_GPIO_PORTS];
42 uint gpio_int_enable[TEGRA_GPIO_PORTS];
43 uint gpio_int_level[TEGRA_GPIO_PORTS];
44 uint gpio_int_clear[TEGRA_GPIO_PORTS];
48 struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
52 GPIO_PA0 = 0, /* pin 0 */
68 GPIO_PC0, /* pin 16 */
76 GPIO_PD0, /* pin 24 */
84 GPIO_PE0, /* pin 32 */
92 GPIO_PF0, /* pin 40 */
100 GPIO_PG0, /* pin 48 */
108 GPIO_PH0, /* pin 56 */
116 GPIO_PI0, /* pin 64 */
124 GPIO_PJ0, /* pin 72 */
132 GPIO_PK0, /* pin 80 */
140 GPIO_PL0, /* pin 88 */
148 GPIO_PM0, /* pin 96 */
156 GPIO_PN0, /* pin 104 */
164 GPIO_PO0, /* pin 112 */
172 GPIO_PP0, /* pin 120 */
180 GPIO_PQ0, /* pin 128 */
188 GPIO_PR0, /* pin 136 */
196 GPIO_PS0, /* pin 144 */
204 GPIO_PT0, /* pin 152 */
212 GPIO_PU0, /* pin 160 */
220 GPIO_PV0, /* pin 168 */
228 GPIO_PW0, /* pin 176 */
236 GPIO_PX0, /* pin 184 */
244 GPIO_PY0, /* pin 192 */
252 GPIO_PZ0, /* pin 200 */
260 GPIO_PAA0, /* pin 208 */
268 GPIO_PBB0, /* pin 216 */
275 GPIO_PBB7, /* pin 223 */
278 #endif /* TEGRA20_GPIO_H_ */