2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 * Pin groups which we adjust. There are three basic attributes of each pin
13 * group which use this enum:
17 * - tristate or normal
20 /* APB_MISC_PP_TRISTATE_REG_A_0 */
57 /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
94 /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
131 /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
150 /* these pin groups only have pullup and pull down control */
152 PINGRP_CK32 = PINGRP_FIRST_NO_MUX,
166 * Functions which can be assigned to each of the pin groups. The values here
167 * bear no relation to the values programmed into pinmux registers and are
168 * purely a convenience. The translation is done through a table search.
173 PMUX_FUNC_AUDIO_SYNC,
182 PMUX_FUNC_EMC_TEST0_DLL,
183 PMUX_FUNC_EMC_TEST1_DLL,
228 PMUX_FUNC_VI_SENSOR_CLK,
232 /* These don't have a name, but can be used in the table */
237 PMUX_FUNC_RSVD, /* Not valid and should not be used */
244 /* return 1 if a pmux_func is in range */
245 #define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \
246 (func) != PMUX_FUNC_RSVD)
248 /* The pullup/pulldown state of a pin group */
250 PMUX_PULL_NORMAL = 0,
255 /* Defines whether a pin group is tristated or in normal operation */
258 PMUX_TRI_TRISTATE = 1,
261 /* Available power domains used by pin groups */
277 PMUX_TRISTATE_REGS = 4,
282 /* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
283 struct pmux_tri_ctlr {
284 uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
285 uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
286 uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
287 uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
288 uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
289 uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */
290 uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
292 uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
294 uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */
295 uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */
296 uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */
300 * This defines the configuration for a pin, including the function assigned,
301 * pull up/down settings and tristate settings. Having set up one of these
302 * you can call pinmux_config_pingroup() to configure a pin in one step. Also
303 * available is pinmux_config_table() to configure a list of pins.
305 struct pingroup_config {
306 enum pmux_pingrp pingroup; /* pin group PINGRP_... */
307 enum pmux_func func; /* function to assign FUNC_... */
308 enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
309 enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
312 /* Set a pin group to tristate */
313 void pinmux_tristate_enable(enum pmux_pingrp pin);
315 /* Set a pin group to normal (non tristate) */
316 void pinmux_tristate_disable(enum pmux_pingrp pin);
318 /* Set the pull up/down feature for a pin group */
319 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
321 /* Set the mux function for a pin group */
322 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
324 /* Set the complete configuration for a pin group */
325 void pinmux_config_pingroup(const struct pingroup_config *config);
327 void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
330 * Configuure a list of pin groups
332 * @param config List of config items
333 * @param len Number of config items in list
335 void pinmux_config_table(const struct pingroup_config *config, int len);
337 #endif /* PINMUX_H */