2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _TEGRA20_PINMUX_H_
9 #define _TEGRA20_PINMUX_H_
12 * Pin groups which we adjust. There are three basic attributes of each pin
13 * group which use this enum:
17 * - tristate or normal
20 /* APB_MISC_PP_TRISTATE_REG_A_0 */
57 /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
94 /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
131 /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
150 /* these pin groups only have pullup and pull down control */
152 PINGRP_CK32 = PINGRP_FIRST_NO_MUX,
166 * Functions which can be assigned to each of the pin groups. The values here
167 * bear no relation to the values programmed into pinmux registers and are
168 * purely a convenience. The translation is done through a table search.
173 PMUX_FUNC_AUDIO_SYNC,
182 PMUX_FUNC_EMC_TEST0_DLL,
183 PMUX_FUNC_EMC_TEST1_DLL,
228 PMUX_FUNC_VI_SENSOR_CLK,
233 PMUX_FUNC_RSVD1 = 0x8000,
234 PMUX_FUNC_RSVD2 = 0x8001,
235 PMUX_FUNC_RSVD3 = 0x8002,
236 PMUX_FUNC_RSVD4 = 0x8003,
239 #include <asm/arch-tegra/pinmux.h>
241 #endif /* _TEGRA20_PINMUX_H_ */