2 * (C) Copyright 2010, 2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _SDRAM_PARAM_H_
9 #define _SDRAM_PARAM_H_
12 * Defines the number of 32-bit words provided in each set of SDRAM parameters
13 * for arbitration configuration data.
15 #define BCT_SDRAM_ARB_CONFIG_WORDS 27
24 MEMORY_TYPE_FORCE32 = 0x7FFFFFFF
27 /* Defines the SDRAM parameter structure */
29 enum memory_type memory_type;
30 u32 pllm_charge_pump_setup_control;
31 u32 pllm_loop_filter_setup_control;
32 u32 pllm_input_divider;
33 u32 pllm_feedback_divider;
34 u32 pllm_post_divider;
36 u32 emc_clock_divider;
37 u32 emc_auto_cal_interval;
38 u32 emc_auto_cal_config;
39 u32 emc_auto_cal_wait;
40 u32 emc_pin_program_wait;
59 u32 emc_burst_refresh_num;
75 u32 emc_fbio_dqsib_dly;
76 u32 emc_fbio_dqsib_dly_msb;
77 u32 emc_fbio_quse_dly;
78 u32 emc_fbio_quse_dly_msb;
87 u32 emc_mrw_reset_command;
88 u32 emc_mrw_reset_init_wait;
92 u32 emc_low_latency_config;
96 u32 ahb_arbitration_xbar_ctrl;
98 u32 emc_dll_xform_dqs;
99 u32 emc_dll_xform_quse;
101 u32 emc_ctt_term_ctrl;
104 u32 emc_zcal_ref_cnt;
105 u32 emc_zcal_wait_cnt;
106 u32 emc_zcal_mrw_cmd;
107 u32 emc_mrs_reset_dll;
108 u32 emc_mrw_zq_init_dev0;
109 u32 emc_mrw_zq_init_dev1;
110 u32 emc_mrw_zq_init_wait;
111 u32 emc_mrs_reset_dll_wait;
114 u32 emc_emrs_ddr2_dll_enable;
115 u32 emc_mrs_ddr2_dll_reset;
116 u32 emc_emrs_ddr2_ocd_calib;
118 u32 emc_cfg_clktrim0;
119 u32 emc_cfg_clktrim1;
120 u32 emc_cfg_clktrim2;
122 u32 apb_misc_gp_xm2cfga_padctrl;
123 u32 apb_misc_gp_xm2cfgc_padctrl;
124 u32 apb_misc_gp_xm2cfgc_padctrl2;
125 u32 apb_misc_gp_xm2cfgd_padctrl;
126 u32 apb_misc_gp_xm2cfgd_padctrl2;
127 u32 apb_misc_gp_xm2clkcfg_padctrl;
128 u32 apb_misc_gp_xm2comp_padctrl;
129 u32 apb_misc_gp_xm2vttgen_padctrl;
130 u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS];