2 * (C) Copyright 2013-2015
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra210 clock PLL tables */
10 #ifndef _TEGRA210_CLOCK_TABLES_H_
11 #define _TEGRA210_CLOCK_TABLES_H_
13 /* The PLLs supported by the hardware */
16 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
23 /* now the simple ones */
24 CLOCK_ID_FIRST_SIMPLE,
25 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
30 /* These are the base clocks (inputs to the Tegra SoC) */
35 CLOCK_ID_COUNT, /* number of PLLs */
38 * These are clock IDs that are used in table clock_source[][]
39 * but will not be assigned as a clock source for any peripheral.
55 /* The clocks supported by the hardware */
59 /* Low word: 31:0 (DEVICES_L) */
60 PERIPH_ID_CPU = PERIPH_ID_FIRST,
99 /* Middle word: 63:32 (DEVICES_H) */
103 PERIPH_ID_RESERVED35,
104 PERIPH_ID_RESERVED36,
106 PERIPH_ID_RESERVED38,
113 PERIPH_ID_RESERVED43,
121 PERIPH_ID_RESERVED49,
125 PERIPH_ID_RESERVED53,
134 PERIPH_ID_RESERVED60,
139 /* Upper word 95:64 (DEVICES_U) */
140 PERIPH_ID_RESERVED64,
155 PERIPH_ID_TRACECLKIN,
160 PERIPH_ID_RESERVED80,
164 PERIPH_ID_RESERVED84,
165 PERIPH_ID_RESERVED85,
166 PERIPH_ID_RESERVED86,
170 PERIPH_ID_RESERVED88,
172 PERIPH_ID_RESERVED90,
174 PERIPH_ID_RESERVED92,
175 PERIPH_ID_RESERVED93,
176 PERIPH_ID_RESERVED94,
181 PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
183 PERIPH_ID_V_RESERVED2,
185 PERIPH_ID_V_RESERVED4,
195 PERIPH_ID_V_RESERVED12,
196 PERIPH_ID_V_RESERVED13,
197 PERIPH_ID_V_RESERVED14,
198 PERIPH_ID_HDA2CODEC2X,
202 PERIPH_ID_V_RESERVED17,
203 PERIPH_ID_V_RESERVED18,
204 PERIPH_ID_V_RESERVED19,
205 PERIPH_ID_V_RESERVED20,
206 PERIPH_ID_V_RESERVED21,
207 PERIPH_ID_V_RESERVED22,
211 PERIPH_ID_EXTPERIPH1,
212 PERIPH_ID_EXTPERIPH2,
213 PERIPH_ID_EXTPERIPH3,
217 PERIPH_ID_V_RESERVED30,
218 PERIPH_ID_V_RESERVED31,
221 PERIPH_ID_HDA2HDMICODEC,
223 PERIPH_ID_W_RESERVED2,
224 PERIPH_ID_W_RESERVED3,
225 PERIPH_ID_W_RESERVED4,
226 PERIPH_ID_W_RESERVED5,
227 PERIPH_ID_W_RESERVED6,
228 PERIPH_ID_W_RESERVED7,
232 PERIPH_ID_W_RESERVED9,
233 PERIPH_ID_W_RESERVED10,
234 PERIPH_ID_W_RESERVED11,
235 PERIPH_ID_W_RESERVED12,
236 PERIPH_ID_W_RESERVED13,
237 PERIPH_ID_XUSB_PADCTL,
238 PERIPH_ID_W_RESERVED15,
241 PERIPH_ID_W_RESERVED16,
242 PERIPH_ID_W_RESERVED17,
243 PERIPH_ID_W_RESERVED18,
244 PERIPH_ID_W_RESERVED19,
245 PERIPH_ID_W_RESERVED20,
248 PERIPH_ID_W_RESERVED23,
251 PERIPH_ID_W_RESERVED24,
252 PERIPH_ID_W_RESERVED25,
253 PERIPH_ID_W_RESERVED26,
256 PERIPH_ID_W_RESERVED29,
257 PERIPH_ID_W_RESERVED30,
258 PERIPH_ID_W_RESERVED31,
262 PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
263 PERIPH_ID_X_RESERVED1,
264 PERIPH_ID_X_RESERVED2,
265 PERIPH_ID_X_RESERVED3,
269 PERIPH_ID_X_RESERVED7,
272 PERIPH_ID_X_RESERVED8,
273 PERIPH_ID_X_RESERVED9,
274 PERIPH_ID_X_RESERVED10,
276 PERIPH_ID_X_RESERVED12,
277 PERIPH_ID_X_RESERVED13,
279 PERIPH_ID_X_RESERVED15,
282 PERIPH_ID_HDMI_AUDIO,
285 PERIPH_ID_X_RESERVED19,
286 PERIPH_ID_X_RESERVED20,
289 PERIPH_ID_X_RESERVED23,
293 PERIPH_ID_X_RESERVED25,
294 PERIPH_ID_X_RESERVED26,
295 PERIPH_ID_X_RESERVED27,
296 PERIPH_ID_X_RESERVED28,
297 PERIPH_ID_X_RESERVED29,
298 PERIPH_ID_X_RESERVED30,
299 PERIPH_ID_X_RESERVED31,
302 /* Y word: 31:0 (192:223) */
303 PERIPH_ID_SPARE1 = PERIPH_ID_Y_FIRST,
304 PERIPH_ID_Y_RESERVED1,
305 PERIPH_ID_Y_RESERVED2,
306 PERIPH_ID_Y_RESERVED3,
307 PERIPH_ID_Y_RESERVED4,
308 PERIPH_ID_Y_RESERVED5,
310 PERIPH_ID_Y_RESERVED7,
314 PERIPH_ID_Y_RESERVED9,
315 PERIPH_ID_Y_RESERVED10,
316 PERIPH_ID_Y_RESERVED11,
317 PERIPH_ID_Y_RESERVED12,
318 PERIPH_ID_PEX_USB_UPHY,
319 PERIPH_ID_Y_RESERVED14,
320 PERIPH_ID_Y_RESERVED15,
324 PERIPH_ID_Y_RESERVED17,
325 PERIPH_ID_Y_RESERVED18,
327 PERIPH_ID_Y_RESERVED20,
328 PERIPH_ID_Y_RESERVED21,
329 PERIPH_ID_Y_RESERVED22,
330 PERIPH_ID_Y_RESERVED23,
333 PERIPH_ID_Y_RESERVED24,
334 PERIPH_ID_Y_RESERVED25,
335 PERIPH_ID_Y_RESERVED26,
336 PERIPH_ID_Y_RESERVED27,
337 PERIPH_ID_Y_RESERVED28,
338 PERIPH_ID_Y_RESERVED29,
339 PERIPH_ID_Y_RESERVED30,
340 PERIPH_ID_Y_RESERVED31,
354 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
355 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
356 * confusion bewteen PERIPH_ID_... and PERIPHC_...
358 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
361 enum periphc_internal_id {
444 PERIPHC_40h = PERIPHC_VW_FIRST,
480 PERIPHC_HDA, /* 0x428 */
485 PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
488 PERIPHC_XUSB_CORE_DEV,
526 PERIPHC_SDMMC_LEGACY_TM = PERIPHC_Y_FIRST, /* 0x694 */
527 PERIPHC_NVDEC, /* 0x698 */
528 PERIPHC_NVJPG, /* 0x69c */
529 PERIPHC_NVENC, /* 0x6a0 */
538 PERIPHC_DMIC3, /* 0x6bc: */
539 PERIPHC_APE, /* 0x6c0: */
540 PERIPHC_QSPI, /* 0x6c4: */
541 PERIPHC_VI_I2C, /* 0x6c8: */
542 PERIPHC_USB2_HSIC_TRK, /* 0x6cc: */
543 PERIPHC_PEX_SATA_USB_RX_BYP, /* 0x6d0: */
546 PERIPHC_MAUD, /* 0x6d4: */
547 PERIPHC_TSECB, /* 0x6d8: */
553 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
554 #define PERIPH_REG(id) \
555 (id < PERIPH_ID_VW_FIRST) ? \
556 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
558 /* Mask value for a clock (within PERIPH_REG(id)) */
559 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
561 /* return 1 if a PLL ID is in range */
562 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
564 /* return 1 if a peripheral ID is in range */
565 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
566 (id) < PERIPH_ID_COUNT)
568 #endif /* _TEGRA210_CLOCK_TABLES_H_ */