1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2013-2015
4 * NVIDIA Corporation <www.nvidia.com>
7 /* Tegra210 clock PLL tables */
9 #ifndef _TEGRA210_CLOCK_TABLES_H_
10 #define _TEGRA210_CLOCK_TABLES_H_
12 /* The PLLs supported by the hardware */
15 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
22 /* now the simple ones */
23 CLOCK_ID_FIRST_SIMPLE,
24 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
29 /* These are the base clocks (inputs to the Tegra SoC) */
34 CLOCK_ID_COUNT, /* number of PLLs */
37 * These are clock IDs that are used in table clock_source[][]
38 * but will not be assigned as a clock source for any peripheral.
54 /* The clocks supported by the hardware */
58 /* Low word: 31:0 (DEVICES_L) */
59 PERIPH_ID_CPU = PERIPH_ID_FIRST,
98 /* Middle word: 63:32 (DEVICES_H) */
102 PERIPH_ID_RESERVED35,
103 PERIPH_ID_RESERVED36,
105 PERIPH_ID_RESERVED38,
112 PERIPH_ID_RESERVED43,
120 PERIPH_ID_RESERVED49,
124 PERIPH_ID_RESERVED53,
133 PERIPH_ID_RESERVED60,
138 /* Upper word 95:64 (DEVICES_U) */
139 PERIPH_ID_RESERVED64,
154 PERIPH_ID_TRACECLKIN,
159 PERIPH_ID_RESERVED80,
163 PERIPH_ID_RESERVED84,
164 PERIPH_ID_RESERVED85,
165 PERIPH_ID_RESERVED86,
169 PERIPH_ID_RESERVED88,
171 PERIPH_ID_RESERVED90,
173 PERIPH_ID_RESERVED92,
174 PERIPH_ID_RESERVED93,
175 PERIPH_ID_RESERVED94,
180 PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
182 PERIPH_ID_V_RESERVED2,
184 PERIPH_ID_V_RESERVED4,
194 PERIPH_ID_V_RESERVED12,
195 PERIPH_ID_V_RESERVED13,
196 PERIPH_ID_V_RESERVED14,
197 PERIPH_ID_HDA2CODEC2X,
201 PERIPH_ID_V_RESERVED17,
202 PERIPH_ID_V_RESERVED18,
203 PERIPH_ID_V_RESERVED19,
204 PERIPH_ID_V_RESERVED20,
205 PERIPH_ID_V_RESERVED21,
206 PERIPH_ID_V_RESERVED22,
210 PERIPH_ID_EXTPERIPH1,
211 PERIPH_ID_EXTPERIPH2,
212 PERIPH_ID_EXTPERIPH3,
216 PERIPH_ID_V_RESERVED30,
217 PERIPH_ID_V_RESERVED31,
220 PERIPH_ID_HDA2HDMICODEC,
222 PERIPH_ID_W_RESERVED2,
223 PERIPH_ID_W_RESERVED3,
224 PERIPH_ID_W_RESERVED4,
225 PERIPH_ID_W_RESERVED5,
226 PERIPH_ID_W_RESERVED6,
227 PERIPH_ID_W_RESERVED7,
231 PERIPH_ID_W_RESERVED9,
232 PERIPH_ID_W_RESERVED10,
233 PERIPH_ID_W_RESERVED11,
234 PERIPH_ID_W_RESERVED12,
235 PERIPH_ID_W_RESERVED13,
236 PERIPH_ID_XUSB_PADCTL,
237 PERIPH_ID_W_RESERVED15,
240 PERIPH_ID_W_RESERVED16,
241 PERIPH_ID_W_RESERVED17,
242 PERIPH_ID_W_RESERVED18,
243 PERIPH_ID_W_RESERVED19,
244 PERIPH_ID_W_RESERVED20,
247 PERIPH_ID_W_RESERVED23,
250 PERIPH_ID_W_RESERVED24,
251 PERIPH_ID_W_RESERVED25,
252 PERIPH_ID_W_RESERVED26,
255 PERIPH_ID_W_RESERVED29,
256 PERIPH_ID_W_RESERVED30,
257 PERIPH_ID_W_RESERVED31,
261 PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
262 PERIPH_ID_X_RESERVED1,
263 PERIPH_ID_X_RESERVED2,
264 PERIPH_ID_X_RESERVED3,
268 PERIPH_ID_X_RESERVED7,
271 PERIPH_ID_X_RESERVED8,
272 PERIPH_ID_X_RESERVED9,
273 PERIPH_ID_X_RESERVED10,
275 PERIPH_ID_X_RESERVED12,
276 PERIPH_ID_X_RESERVED13,
278 PERIPH_ID_X_RESERVED15,
281 PERIPH_ID_HDMI_AUDIO,
284 PERIPH_ID_X_RESERVED19,
285 PERIPH_ID_X_RESERVED20,
288 PERIPH_ID_X_RESERVED23,
292 PERIPH_ID_X_RESERVED25,
293 PERIPH_ID_X_RESERVED26,
294 PERIPH_ID_X_RESERVED27,
295 PERIPH_ID_X_RESERVED28,
296 PERIPH_ID_X_RESERVED29,
297 PERIPH_ID_X_RESERVED30,
298 PERIPH_ID_X_RESERVED31,
301 /* Y word: 31:0 (192:223) */
302 PERIPH_ID_SPARE1 = PERIPH_ID_Y_FIRST,
303 PERIPH_ID_Y_RESERVED1,
304 PERIPH_ID_Y_RESERVED2,
305 PERIPH_ID_Y_RESERVED3,
306 PERIPH_ID_Y_RESERVED4,
307 PERIPH_ID_Y_RESERVED5,
309 PERIPH_ID_Y_RESERVED7,
313 PERIPH_ID_Y_RESERVED9,
314 PERIPH_ID_Y_RESERVED10,
315 PERIPH_ID_Y_RESERVED11,
316 PERIPH_ID_Y_RESERVED12,
317 PERIPH_ID_PEX_USB_UPHY,
318 PERIPH_ID_Y_RESERVED14,
319 PERIPH_ID_Y_RESERVED15,
323 PERIPH_ID_Y_RESERVED17,
324 PERIPH_ID_Y_RESERVED18,
326 PERIPH_ID_Y_RESERVED20,
327 PERIPH_ID_Y_RESERVED21,
328 PERIPH_ID_Y_RESERVED22,
329 PERIPH_ID_Y_RESERVED23,
332 PERIPH_ID_Y_RESERVED24,
333 PERIPH_ID_Y_RESERVED25,
334 PERIPH_ID_Y_RESERVED26,
335 PERIPH_ID_Y_RESERVED27,
336 PERIPH_ID_Y_RESERVED28,
337 PERIPH_ID_Y_RESERVED29,
338 PERIPH_ID_Y_RESERVED30,
339 PERIPH_ID_Y_RESERVED31,
353 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
354 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
355 * confusion bewteen PERIPH_ID_... and PERIPHC_...
357 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
360 enum periphc_internal_id {
443 PERIPHC_40h = PERIPHC_VW_FIRST,
479 PERIPHC_HDA, /* 0x428 */
484 PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
487 PERIPHC_XUSB_CORE_DEV,
525 PERIPHC_SDMMC_LEGACY_TM = PERIPHC_Y_FIRST, /* 0x694 */
526 PERIPHC_NVDEC, /* 0x698 */
527 PERIPHC_NVJPG, /* 0x69c */
528 PERIPHC_NVENC, /* 0x6a0 */
537 PERIPHC_DMIC3, /* 0x6bc: */
538 PERIPHC_APE, /* 0x6c0: */
539 PERIPHC_QSPI, /* 0x6c4: */
540 PERIPHC_VI_I2C, /* 0x6c8: */
541 PERIPHC_USB2_HSIC_TRK, /* 0x6cc: */
542 PERIPHC_PEX_SATA_USB_RX_BYP, /* 0x6d0: */
545 PERIPHC_MAUD, /* 0x6d4: */
546 PERIPHC_TSECB, /* 0x6d8: */
552 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
553 #define PERIPH_REG(id) \
554 (id < PERIPH_ID_VW_FIRST) ? \
555 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
557 /* Mask value for a clock (within PERIPH_REG(id)) */
558 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
560 /* return 1 if a PLL ID is in range */
561 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
563 /* return 1 if a peripheral ID is in range */
564 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
565 (id) < PERIPH_ID_COUNT)
567 #endif /* _TEGRA210_CLOCK_TABLES_H_ */