2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra30 clock PLL tables */
19 #ifndef _TEGRA30_CLOCK_TABLES_H_
20 #define _TEGRA30_CLOCK_TABLES_H_
22 /* The PLLs supported by the hardware */
25 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
32 /* now the simple ones */
33 CLOCK_ID_FIRST_SIMPLE,
34 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
38 /* These are the base clocks (inputs to the Tegra SOC) */
43 CLOCK_ID_COUNT, /* number of PLLs */
44 CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
48 /* The clocks supported by the hardware */
53 PERIPH_ID_CPU = PERIPH_ID_FIRST,
92 /* Middle word: 63:32 */
106 PERIPH_ID_RESERVED43,
108 PERIPH_ID_RESERVED45,
123 PERIPH_ID_RESERVED56,
132 /* Upper word 95:64 */
147 PERIPH_ID_RESERVED76,
148 PERIPH_ID_RESERVED77,
149 PERIPH_ID_RESERVED78,
156 PERIPH_ID_RESERVED83,
164 PERIPH_ID_RESERVED89,
166 PERIPH_ID_RESERVED91,
168 PERIPH_ID_RESERVED93,
169 PERIPH_ID_RESERVED94,
170 PERIPH_ID_RESERVED95,
174 PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
191 PERIPH_ID_HDA2CODEC2X,
195 PERIPH_ID_EX_RESERVED17,
196 PERIPH_ID_EX_RESERVED18,
197 PERIPH_ID_EX_RESERVED19,
198 PERIPH_ID_EX_RESERVED20,
199 PERIPH_ID_EX_RESERVED21,
200 PERIPH_ID_EX_RESERVED22,
204 PERIPH_ID_EX_RESERVED24,
205 PERIPH_ID_EX_RESERVED25,
206 PERIPH_ID_EX_RESERVED26,
207 PERIPH_ID_EX_RESERVED27,
210 PERIPH_ID_EX_RESERVED30,
211 PERIPH_ID_EX_RESERVED31,
214 PERIPH_ID_HDA2HDMICODEC,
216 PERIPH_ID_RESERVED0_PCIERX0,
217 PERIPH_ID_RESERVED1_PCIERX1,
218 PERIPH_ID_RESERVED2_PCIERX2,
219 PERIPH_ID_RESERVED3_PCIERX3,
220 PERIPH_ID_RESERVED4_PCIERX4,
221 PERIPH_ID_RESERVED5_PCIERX5,
225 PERIPH_ID_RESERVED6_PCIE2,
226 PERIPH_ID_RESERVED7_EMC,
227 PERIPH_ID_RESERVED8_HDMI,
228 PERIPH_ID_RESERVED9_SATA,
229 PERIPH_ID_RESERVED10_MIPI,
230 PERIPH_ID_EX_RESERVED46,
231 PERIPH_ID_EX_RESERVED47,
245 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
246 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
247 * confusion bewteen PERIPH_ID_... and PERIPHC_...
249 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
252 enum periphc_internal_id {
325 PERIPHC_G3D2 = PERIPHC_VW_FIRST,
368 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
369 #define PERIPH_REG(id) \
370 (id < PERIPH_ID_VW_FIRST) ? \
371 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
373 /* Mask value for a clock (within PERIPH_REG(id)) */
374 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
376 /* return 1 if a PLL ID is in range */
377 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
379 /* return 1 if a peripheral ID is in range */
380 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
381 (id) < PERIPH_ID_COUNT)
383 #endif /* _TEGRA30_CLOCK_TABLES_H_ */