2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #ifndef _TEGRA30_PINMUX_H_
18 #define _TEGRA30_PINMUX_H_
21 * Pin groups which we adjust. There are three basic attributes of each pin
22 * group which use this enum:
26 * - tristate or normal
29 PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
267 PINGRP_PEX_L0_PRSNT_N,
269 PINGRP_PEX_L0_CLKREQ_N,
271 PINGRP_PEX_L1_PRSNT_N,
273 PINGRP_PEX_L1_CLKREQ_N,
274 PINGRP_PEX_L2_PRSNT_N,
276 PINGRP_PEX_L2_CLKREQ_N,
277 PINGRP_HDMI_CEC, /* offset 0x33e0 */
282 PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
289 PDRIVE_PINGROUP_CDEV1,
290 PDRIVE_PINGROUP_CDEV2,
291 PDRIVE_PINGROUP_CSUS,
292 PDRIVE_PINGROUP_DAP1,
293 PDRIVE_PINGROUP_DAP2,
294 PDRIVE_PINGROUP_DAP3,
295 PDRIVE_PINGROUP_DAP4,
297 PDRIVE_PINGROUP_LCD1,
298 PDRIVE_PINGROUP_LCD2,
299 PDRIVE_PINGROUP_SDIO2,
300 PDRIVE_PINGROUP_SDIO3,
304 PDRIVE_PINGROUP_UART2,
305 PDRIVE_PINGROUP_UART3,
306 PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
307 PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
308 PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
321 PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
322 PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
323 PDRIVE_PINGROUP_COUNT,
327 * Functions which can be assigned to each of the pin groups. The values here
328 * bear no relation to the values programmed into pinmux registers and are
329 * purely a convenience. The translation is done through a table search.
334 PMUX_FUNC_AUDIO_SYNC,
343 PMUX_FUNC_EMC_TEST0_DLL,
344 PMUX_FUNC_EMC_TEST1_DLL,
389 PMUX_FUNC_VI_SENSOR_CLK,
403 PMUX_FUNC_EXTPERIPH1,
404 PMUX_FUNC_EXTPERIPH2,
405 PMUX_FUNC_EXTPERIPH3,
434 PMUX_FUNC_CLK_12M_OUT,
437 PMUX_FUNC_CORE_PWR_REQ,
438 PMUX_FUNC_CPU_PWR_REQ,
440 PMUX_FUNC_CLK_32K_IN,
445 PMUX_FUNC_RSVD1 = 0x8000,
446 PMUX_FUNC_RSVD2 = 0x8001,
447 PMUX_FUNC_RSVD3 = 0x8002,
448 PMUX_FUNC_RSVD4 = 0x8003,
451 /* return 1 if a pmux_func is in range */
452 #define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
453 || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
455 /* return 1 if a pingrp is in range */
456 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
458 /* The pullup/pulldown state of a pin group */
460 PMUX_PULL_NORMAL = 0,
464 /* return 1 if a pin_pupd_is in range */
465 #define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
466 ((pupd) <= PMUX_PULL_UP))
468 /* Defines whether a pin group is tristated or in normal operation */
471 PMUX_TRI_TRISTATE = 1,
473 /* return 1 if a pin_tristate_is in range */
474 #define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
475 && ((tristate) <= PMUX_TRI_TRISTATE))
481 /* return 1 if a pin_io_is in range */
482 #define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
483 ((io) <= PMUX_PIN_INPUT))
486 PMUX_PIN_LOCK_DEFAULT = 0,
487 PMUX_PIN_LOCK_DISABLE,
488 PMUX_PIN_LOCK_ENABLE,
490 /* return 1 if a pin_lock is in range */
491 #define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
492 ((lock) <= PMUX_PIN_LOCK_ENABLE))
495 PMUX_PIN_OD_DEFAULT = 0,
499 /* return 1 if a pin_od is in range */
500 #define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
501 ((od) <= PMUX_PIN_OD_ENABLE))
503 enum pmux_pin_ioreset {
504 PMUX_PIN_IO_RESET_DEFAULT = 0,
505 PMUX_PIN_IO_RESET_DISABLE,
506 PMUX_PIN_IO_RESET_ENABLE,
508 /* return 1 if a pin_ioreset_is in range */
509 #define pmux_pin_ioreset_isvalid(ioreset) \
510 (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
511 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
513 /* Available power domains used by pin groups */
534 #define PGRP_SLWF_NONE -1
535 #define PGRP_SLWF_MAX 3
536 #define PGRP_SLWR_NONE PGRP_SLWF_NONE
537 #define PGRP_SLWR_MAX PGRP_SLWF_MAX
539 #define PGRP_DRVUP_NONE -1
540 #define PGRP_DRVUP_MAX 127
541 #define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
542 #define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
544 /* return 1 if a padgrp is in range */
545 #define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
547 /* return 1 if a slew-rate rising/falling edge value is in range */
548 #define pmux_pad_slw_isvalid(slw) (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))
550 /* return 1 if a driver output pull-up/down strength code value is in range */
551 #define pmux_pad_drv_isvalid(drv) (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))
553 /* return 1 if a low-power mode value is in range */
554 #define pmux_pad_lpmd_isvalid(lpm) (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))
556 /* Defines a pin group cfg's low-power mode select */
565 /* Defines whether a pin group cfg's schmidt is enabled or not */
567 PGRP_SCHMT_DISABLE = 0,
568 PGRP_SCHMT_ENABLE = 1,
571 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
573 PGRP_HSM_DISABLE = 0,
578 * This defines the configuration for a pin group's pad control config
580 struct padctrl_config {
581 enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
582 int slwf; /* falling edge slew */
583 int slwr; /* rising edge slew */
584 int drvup; /* pull-up drive strength */
585 int drvdn; /* pull-down drive strength */
586 enum pgrp_lpmd lpmd; /* low-power mode selection */
587 enum pgrp_schmt schmt; /* schmidt enable */
588 enum pgrp_hsm hsm; /* high-speed mode enable */
591 /* t30 pin drive group and pin mux registers */
592 #define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
593 #define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
594 PDRIVE_PINGROUP_COUNT)
595 struct pmux_tri_ctlr {
596 uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
597 uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
598 uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
599 uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
600 uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
601 uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
602 uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
604 uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
606 uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
607 uint pmt_reserved5[PMUX_OFFSET];
608 uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
612 * This defines the configuration for a pin, including the function assigned,
613 * pull up/down settings and tristate settings. Having set up one of these
614 * you can call pinmux_config_pingroup() to configure a pin in one step. Also
615 * available is pinmux_config_table() to configure a list of pins.
617 struct pingroup_config {
618 enum pmux_pingrp pingroup; /* pin group PINGRP_... */
619 enum pmux_func func; /* function to assign FUNC_... */
620 enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
621 enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
622 enum pmux_pin_io io; /* input or output PMUX_PIN_... */
623 enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
624 enum pmux_pin_od od; /* open-drain or push-pull driver */
625 enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
628 /* Set a pin group to tristate */
629 void pinmux_tristate_enable(enum pmux_pingrp pin);
631 /* Set a pin group to normal (non tristate) */
632 void pinmux_tristate_disable(enum pmux_pingrp pin);
634 /* Set the pull up/down feature for a pin group */
635 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
637 /* Set the mux function for a pin group */
638 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
640 /* Set the complete configuration for a pin group */
641 void pinmux_config_pingroup(struct pingroup_config *config);
643 /* Set a pin group to tristate or normal */
644 void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
646 /* Set a pin group as input or output */
647 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
650 * Configure a list of pin groups
652 * @param config List of config items
653 * @param len Number of config items in list
655 void pinmux_config_table(struct pingroup_config *config, int len);
657 /* Set a group of pins from a table */
658 void pinmux_init(void);
661 * Set the GP pad configs
663 * @param config List of config items
664 * @param len Number of config items in list
666 void padgrp_config_table(struct padctrl_config *config, int len);
668 #endif /* _TEGRA30_PINMUX_H_ */