1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
7 #define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
11 #include <linux/types.h>
13 /* Clock Controller Module (CCM) */
57 /* Analog components control digital interface (ANADIG) */
59 u32 reserved_0x000[4];
61 u32 reserved_0x014[3];
63 u32 reserved_0x024[3];
65 u32 reserved_0x034[3];
67 u32 reserved_0x044[3];
69 u32 reserved_0x054[3];
71 u32 reserved_0x064[3];
73 u32 reserved_0x074[3];
75 u32 reserved_0x084[3];
77 u32 reserved_0x094[3];
79 u32 reserved_0x0A4[3];
81 u32 reserved_0x0B4[3];
83 u32 reserved_0x0C4[7];
85 u32 reserved_0x0E4[3];
87 u32 reserved_0x0F4[3];
89 u32 reserved_0x104[3];
91 u32 reserved_0x114[3];
93 u32 reserved_0x124[3];
95 u32 reserved_0x134[7];
97 u32 reserved_0x154[3];
99 u32 reserved_0x164[63];
101 u32 reserved_0x264[3];
103 u32 reserved_0x274[3];
105 u32 reserved_0x284[3];
107 u32 reserved_0x294[3];
109 u32 reserved_0x2A4[3];
111 u32 reserved_0x2B4[3];
116 #define CCM_CCR_FIRC_EN (1 << 16)
117 #define CCM_CCR_OSCNT_MASK 0xff
118 #define CCM_CCR_OSCNT(v) ((v) & 0xff)
120 #define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
121 #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
122 #define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
124 #define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
125 #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
126 #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
128 #define CCM_CCSR_PLL2_PFD4_EN (1 << 15)
129 #define CCM_CCSR_PLL2_PFD3_EN (1 << 14)
130 #define CCM_CCSR_PLL2_PFD2_EN (1 << 13)
131 #define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
132 #define CCM_CCSR_PLL1_PFD4_EN (1 << 11)
133 #define CCM_CCSR_PLL1_PFD3_EN (1 << 10)
134 #define CCM_CCSR_PLL1_PFD2_EN (1 << 9)
135 #define CCM_CCSR_PLL1_PFD1_EN (1 << 8)
137 #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6)
138 #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5)
140 #define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
141 #define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
142 #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
144 #define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
145 #define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
146 #define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
147 #define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
148 #define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
149 #define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3)
150 #define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
151 #define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
152 #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
154 #define CCM_CSCMR1_DCU1_CLK_SEL (1 << 29)
155 #define CCM_CSCMR1_DCU0_CLK_SEL (1 << 28)
157 #define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22
158 #define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
159 #define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22)
160 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
161 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
162 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
163 #define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12
164 #define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12)
165 #define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12)
167 #define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
169 #define CCM_CSCDR2_NFC_EN (1 << 9)
170 #define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13)
171 #define CCM_CSCDR2_NFC_CLK_INV (1 << 14)
172 #define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4
173 #define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4)
174 #define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4)
176 #define CCM_CSCDR2_ESDHC1_EN (1 << 29)
177 #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
178 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
179 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
181 #define CCM_CSCDR3_DCU1_EN (1 << 23)
182 #define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20)
183 #define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20)
184 #define CCM_CSCDR3_DCU0_EN (1 << 19)
185 #define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16)
186 #define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16)
188 #define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13
189 #define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13)
190 #define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13)
191 #define CCM_CSCDR3_QSPI0_EN (1 << 4)
192 #define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3)
193 #define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2)
194 #define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3)
196 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
197 #define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
198 #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
200 #define CCM_REG_CTRL_MASK 0xffffffff
201 #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
202 #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
203 #define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24)
204 #define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
205 #define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
206 #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
207 #define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26)
208 #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
209 #define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
210 #define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
211 #define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
212 #define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
213 #define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22)
214 #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
215 #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
216 #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
217 #define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4)
218 #define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16)
219 #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
220 #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
221 #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
222 #define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
223 #define CCM_CCGR4_I2C1_CTRL_MASK (0x3 << 14)
224 #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
225 #define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24)
226 #define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26)
227 #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
228 #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
229 #define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)
230 #define CCM_CCGR9_FEC0_CTRL_MASK 0x3
231 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
232 #define CCM_CCGR10_NFC_CTRL_MASK 0x3
233 #define CCM_CCGR10_I2C2_CTRL_MASK (0x3 << 12)
234 #define CCM_CCGR10_I2C3_CTRL_MASK (0x3 << 14)
236 #define ANADIG_PLL7_CTRL_BYPASS (1 << 16)
237 #define ANADIG_PLL7_CTRL_ENABLE (1 << 13)
238 #define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12)
239 #define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1)
240 #define ANADIG_PLL5_CTRL_BYPASS (1 << 16)
241 #define ANADIG_PLL5_CTRL_ENABLE (1 << 13)
242 #define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12)
243 #define ANADIG_PLL5_CTRL_DIV_SELECT 1
244 #define ANADIG_PLL3_CTRL_BYPASS (1 << 16)
245 #define ANADIG_PLL3_CTRL_ENABLE (1 << 13)
246 #define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12)
247 #define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1)
248 #define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
249 #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
250 #define ANADIG_PLL2_CTRL_DIV_SELECT 1
251 #define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
252 #define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
253 #define ANADIG_PLL1_CTRL_DIV_SELECT 1
255 #define FASE_CLK_FREQ 24000000
256 #define SLOW_CLK_FREQ 32000
257 #define PLL1_PFD1_FREQ 500000000
258 #define PLL1_PFD2_FREQ 452000000
259 #define PLL1_PFD3_FREQ 396000000
260 #define PLL1_PFD4_FREQ 528000000
261 #define PLL1_MAIN_FREQ 528000000
262 #define PLL2_PFD1_FREQ 500000000
263 #define PLL2_PFD2_FREQ 396000000
264 #define PLL2_PFD3_FREQ 339000000
265 #define PLL2_PFD4_FREQ 413000000
266 #define PLL2_MAIN_FREQ 528000000
267 #define PLL3_MAIN_FREQ 480000000
268 #define PLL3_PFD3_FREQ 298000000
269 #define PLL5_MAIN_FREQ 500000000
271 #define ENET_EXTERNAL_CLK 50000000
272 #define AUDIO_EXTERNAL_CLK 24576000
274 #endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */