2 * Copyright (c) 2013 Xilinx Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef _ASM_ARCH_HARDWARE_H
24 #define _ASM_ARCH_HARDWARE_H
26 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
27 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
28 #define ZYNQ_SCU_BASEADDR 0xF8F00000
29 #define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
30 #define ZYNQ_GEM_BASEADDR0 0xE000B000
31 #define ZYNQ_GEM_BASEADDR1 0xE000C000
32 #define ZYNQ_SDHCI_BASEADDR0 0xE0100000
33 #define ZYNQ_SDHCI_BASEADDR1 0xE0101000
34 #define ZYNQ_I2C_BASEADDR0 0xE0004000
35 #define ZYNQ_I2C_BASEADDR1 0xE0005000
37 /* Reflect slcr offsets */
40 u32 slcr_lock; /* 0x4 */
41 u32 slcr_unlock; /* 0x8 */
43 u32 gem0_rclk_ctrl; /* 0x138 */
44 u32 gem1_rclk_ctrl; /* 0x13c */
45 u32 gem0_clk_ctrl; /* 0x140 */
46 u32 gem1_clk_ctrl; /* 0x144 */
48 u32 pss_rst_ctrl; /* 0x200 */
50 u32 fpga_rst_ctrl; /* 0x240 */
52 u32 reboot_status; /* 0x258 */
53 u32 boot_mode; /* 0x25c */
55 u32 trust_zone; /* 0x430 */ /* FIXME */
57 u32 pss_idcode; /* 0x530 */
59 u32 ddr_urgent; /* 0x600 */
61 u32 ddr_urgent_sel; /* 0x61c */
63 u32 mio_pin[54]; /* 0x700 - 0x7D4 */
65 u32 lvl_shftr_en; /* 0x900 */
67 u32 ocm_cfg; /* 0x910 */
70 #define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
76 u32 int_sts; /* 0xc */
77 u32 int_mask; /* 0x10 */
78 u32 status; /* 0x14 */
79 u32 dma_src_addr; /* 0x18 */
80 u32 dma_dst_addr; /* 0x1c */
81 u32 dma_src_len; /* 0x20 */
82 u32 dma_dst_len; /* 0x24 */
83 u32 rom_shadow; /* 0x28 */
85 u32 unlock; /* 0x34 */
89 u32 write_count; /* 0x88 */
90 u32 read_count; /* 0x8c */
93 #define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
97 u32 filter_start; /* 0x40 */
98 u32 filter_end; /* 0x44 */
101 #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
103 #endif /* _ASM_ARCH_HARDWARE_H */