2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _ASM_ARCH_HARDWARE_H
9 #define _ASM_ARCH_HARDWARE_H
11 #define ZYNQ_SERIAL_BASEADDR0 0xFF000000
12 #define ZYNQ_SERIAL_BASEADDR1 0xFF001000
14 #define ZYNQ_SDHCI_BASEADDR0 0xFF160000
15 #define ZYNQ_SDHCI_BASEADDR1 0xFF170000
17 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
18 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
22 u32 timestamp_ref_ctrl; /* 0x128 */
24 u32 boot_mode; /* 0x200 */
28 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
30 #define ZYNQMP_IOU_SCNTR 0xFF250000
31 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
32 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
35 u32 counter_control_register;
37 u32 base_frequency_id_register;
40 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
42 /* Bootmode setting values */
43 #define BOOT_MODES_MASK 0x0000000F
44 #define SD_MODE 0x00000005
45 #define JTAG_MODE 0x00000000
47 /* Board version value */
48 #define ZYNQMP_CSU_VERSION_SILICON 0x0
49 #define ZYNQMP_CSU_VERSION_EP108 0x1
50 #define ZYNQMP_CSU_VERSION_QEMU 0x3
52 #endif /* _ASM_ARCH_HARDWARE_H */