2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _ASM_ARCH_HARDWARE_H
9 #define _ASM_ARCH_HARDWARE_H
11 #define ZYNQ_SERIAL_BASEADDR0 0xFF000000
12 #define ZYNQ_SERIAL_BASEADDR1 0xFF001000
14 #define ZYNQ_SPI_BASEADDR0 0xFF040000
15 #define ZYNQ_SPI_BASEADDR1 0xFF050000
17 #define ZYNQ_I2C_BASEADDR0 0xFF020000
18 #define ZYNQ_I2C_BASEADDR1 0xFF030000
20 #define ZYNQ_SDHCI_BASEADDR0 0xFF160000
21 #define ZYNQ_SDHCI_BASEADDR1 0xFF170000
23 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
24 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
28 u32 cpu_r5_ctrl; /* 0x90 */
30 u32 timestamp_ref_ctrl; /* 0x128 */
32 u32 boot_mode; /* 0x200 */
34 u32 rst_lpd_top; /* 0x23C */
38 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
40 #define ZYNQMP_IOU_SCNTR 0xFF250000
41 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
42 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
45 u32 counter_control_register;
47 u32 base_frequency_id_register;
50 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
52 /* Bootmode setting values */
53 #define BOOT_MODES_MASK 0x0000000F
54 #define SD_MODE 0x00000003
55 #define EMMC_MODE 0x00000006
56 #define JTAG_MODE 0x00000000
58 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000
63 u32 rpu0_cfg; /* 0x100 */
65 u32 rpu1_cfg; /* 0x200 */
68 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
70 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
74 u32 rst_fpd_apu; /* 0x104 */
78 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
80 #define ZYNQMP_APU_BASEADDR 0xFD5C0000
84 u32 rvbar_addr0_l; /* 0x40 */
85 u32 rvbar_addr0_h; /* 0x44 */
89 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
91 /* Board version value */
92 #define ZYNQMP_CSU_VERSION_SILICON 0x0
93 #define ZYNQMP_CSU_VERSION_EP108 0x1
94 #define ZYNQMP_CSU_VERSION_VELOCE 0x2
95 #define ZYNQMP_CSU_VERSION_QEMU 0x3
97 #endif /* _ASM_ARCH_HARDWARE_H */