2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _ASM_ARCH_HARDWARE_H
9 #define _ASM_ARCH_HARDWARE_H
11 #define ZYNQ_GEM_BASEADDR0 0xFF0B0000
12 #define ZYNQ_GEM_BASEADDR1 0xFF0C0000
13 #define ZYNQ_GEM_BASEADDR2 0xFF0D0000
14 #define ZYNQ_GEM_BASEADDR3 0xFF0E0000
16 #define ZYNQ_SPI_BASEADDR0 0xFF040000
17 #define ZYNQ_SPI_BASEADDR1 0xFF050000
19 #define ZYNQ_I2C_BASEADDR0 0xFF020000
20 #define ZYNQ_I2C_BASEADDR1 0xFF030000
22 #define ARASAN_NAND_BASEADDR 0xFF100000
24 #define ZYNQMP_SATA_BASEADDR 0xFD0C0000
26 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000
27 #define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000
29 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
30 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
34 u32 cpu_r5_ctrl; /* 0x90 */
36 u32 timestamp_ref_ctrl; /* 0x128 */
38 u32 boot_mode; /* 0x200 */
40 u32 rst_lpd_top; /* 0x23C */
44 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
46 #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000
47 #define ZYNQMP_IOU_SCNTR 0xFF250000
48 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
49 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
52 u32 counter_control_register;
54 u32 base_frequency_id_register;
57 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
59 struct iou_scntr_secure {
60 u32 counter_control_register;
62 u32 base_frequency_id_register;
65 #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
67 /* Bootmode setting values */
68 #define BOOT_MODES_MASK 0x0000000F
69 #define QSPI_MODE_24BIT 0x00000001
70 #define QSPI_MODE_32BIT 0x00000002
71 #define SD_MODE 0x00000003 /* sd 0 */
72 #define SD_MODE1 0x00000005 /* sd 1 */
73 #define NAND_MODE 0x00000004
74 #define EMMC_MODE 0x00000006
75 #define JTAG_MODE 0x00000000
77 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
79 struct iou_slcr_regs {
84 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
86 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000
91 u32 rpu0_cfg; /* 0x100 */
93 u32 rpu1_cfg; /* 0x200 */
96 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
98 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
102 u32 rst_fpd_apu; /* 0x104 */
106 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
108 #define ZYNQMP_APU_BASEADDR 0xFD5C0000
112 u32 rvbar_addr0_l; /* 0x40 */
113 u32 rvbar_addr0_h; /* 0x44 */
117 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
119 /* Board version value */
120 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000
121 #define ZYNQMP_CSU_VERSION_SILICON 0x0
122 #define ZYNQMP_CSU_VERSION_EP108 0x1
123 #define ZYNQMP_CSU_VERSION_VELOCE 0x2
124 #define ZYNQMP_CSU_VERSION_QEMU 0x3
126 #define ZYNQMP_SILICON_VER_MASK 0xF000
127 #define ZYNQMP_SILICON_VER_SHIFT 12
134 #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
136 #endif /* _ASM_ARCH_HARDWARE_H */