1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
7 #ifndef _ASM_ARCH_HARDWARE_H
8 #define _ASM_ARCH_HARDWARE_H
10 #define ZYNQ_GEM_BASEADDR0 0xFF0B0000
11 #define ZYNQ_GEM_BASEADDR1 0xFF0C0000
12 #define ZYNQ_GEM_BASEADDR2 0xFF0D0000
13 #define ZYNQ_GEM_BASEADDR3 0xFF0E0000
15 #define ZYNQ_I2C_BASEADDR0 0xFF020000
16 #define ZYNQ_I2C_BASEADDR1 0xFF030000
18 #define ARASAN_NAND_BASEADDR 0xFF100000
20 #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000
21 #define ZYNQMP_TCM_SIZE 0x40000
23 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
24 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
25 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
26 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8
28 #define PS_MODE0 BIT(0)
29 #define PS_MODE1 BIT(1)
30 #define PS_MODE2 BIT(2)
31 #define PS_MODE3 BIT(3)
33 #define RESET_REASON_DEBUG_SYS BIT(6)
34 #define RESET_REASON_SOFT BIT(5)
35 #define RESET_REASON_SRST BIT(4)
36 #define RESET_REASON_PSONLY BIT(3)
37 #define RESET_REASON_PMU BIT(2)
38 #define RESET_REASON_INTERNAL BIT(1)
39 #define RESET_REASON_EXTERNAL BIT(0)
43 u32 cpu_r5_ctrl; /* 0x90 */
45 u32 timestamp_ref_ctrl; /* 0x128 */
47 u32 boot_mode; /* 0x200 */
49 u32 reset_reason; /* 0x220 */
51 u32 rst_lpd_top; /* 0x23C */
53 u32 boot_pin_ctrl; /* 0x250 */
57 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
59 #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000
60 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
61 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
63 struct iou_scntr_secure {
64 u32 counter_control_register;
66 u32 base_frequency_id_register;
69 #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
71 /* Bootmode setting values */
72 #define BOOT_MODES_MASK 0x0000000F
73 #define QSPI_MODE_24BIT 0x00000001
74 #define QSPI_MODE_32BIT 0x00000002
75 #define SD_MODE 0x00000003 /* sd 0 */
76 #define SD_MODE1 0x00000005 /* sd 1 */
77 #define NAND_MODE 0x00000004
78 #define EMMC_MODE 0x00000006
79 #define USB_MODE 0x00000007
80 #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
81 #define JTAG_MODE 0x00000000
82 #define BOOT_MODE_USE_ALT 0x100
83 #define BOOT_MODE_ALT_SHIFT 12
84 /* SW secondary boot modes 0xa - 0xd */
85 #define SW_USBHOST_MODE 0x0000000A
86 #define SW_SATA_MODE 0x0000000B
88 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
90 struct iou_slcr_regs {
95 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
97 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000
102 u32 rpu0_cfg; /* 0x100 */
104 u32 rpu1_cfg; /* 0x200 */
107 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
109 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
113 u32 rst_fpd_apu; /* 0x104 */
117 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
119 #define ZYNQMP_APU_BASEADDR 0xFD5C0000
123 u32 rvbar_addr0_l; /* 0x40 */
124 u32 rvbar_addr0_h; /* 0x44 */
128 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
130 /* Board version value */
131 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000
132 #define ZYNQMP_CSU_VERSION_SILICON 0x0
133 #define ZYNQMP_CSU_VERSION_QEMU 0x3
135 #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20
137 #define ZYNQMP_SILICON_VER_MASK 0xF000
138 #define ZYNQMP_SILICON_VER_SHIFT 12
145 #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
147 #define ZYNQMP_PMU_BASEADDR 0xFFD80000
151 u32 gen_storage6; /* 0x48 */
154 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
156 #define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040
157 #define ZYNQMP_CSU_VER_ADDR 0xFFCA0044
159 #endif /* _ASM_ARCH_HARDWARE_H */