3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _ASM_ARMV8_MMU_H_
9 #define _ASM_ARMV8_MMU_H_
11 /***************************************************************/
13 * The following definitions are related each other, shoud be
14 * calculated specifically.
17 #define VA_BITS CONFIG_SYS_VA_BITS
18 #define PTE_BLOCK_BITS CONFIG_SYS_PTL2_BITS
21 * block/section address mask and size definitions.
24 /* PAGE_SHIFT determines the page size */
27 #define PAGE_SIZE (1 << PAGE_SHIFT)
28 #define PAGE_MASK (~(PAGE_SIZE-1))
30 /***************************************************************/
35 #define MT_DEVICE_NGNRNE 0
36 #define MT_DEVICE_NGNRE 1
37 #define MT_DEVICE_GRE 2
38 #define MT_NORMAL_NC 3
41 #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
42 (0x04 << (MT_DEVICE_NGNRE * 8)) | \
43 (0x0c << (MT_DEVICE_GRE * 8)) | \
44 (0x44 << (MT_NORMAL_NC * 8)) | \
45 (UL(0xff) << (MT_NORMAL * 8)))
48 * Hardware page table definitions.
52 #define PTE_TYPE_MASK (3 << 0)
53 #define PTE_TYPE_FAULT (0 << 0)
54 #define PTE_TYPE_TABLE (3 << 0)
55 #define PTE_TYPE_BLOCK (1 << 0)
56 #define PTE_TYPE_VALID (1 << 0)
58 #define PTE_TABLE_PXN (1UL << 59)
59 #define PTE_TABLE_XN (1UL << 60)
60 #define PTE_TABLE_AP (1UL << 61)
61 #define PTE_TABLE_NS (1UL << 63)
66 #define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
67 #define PTE_BLOCK_NS (1 << 5)
68 #define PTE_BLOCK_NON_SHARE (0 << 8)
69 #define PTE_BLOCK_OUTER_SHARE (2 << 8)
70 #define PTE_BLOCK_INNER_SHARE (3 << 8)
71 #define PTE_BLOCK_AF (1 << 10)
72 #define PTE_BLOCK_NG (1 << 11)
73 #define PTE_BLOCK_PXN (UL(1) << 53)
74 #define PTE_BLOCK_UXN (UL(1) << 54)
79 #define PMD_ATTRINDX(t) ((t) << 2)
80 #define PMD_ATTRINDX_MASK (7 << 2)
81 #define PMD_ATTRMASK (PTE_BLOCK_PXN | \
89 #define TCR_T0SZ(x) ((64 - (x)) << 0)
90 #define TCR_IRGN_NC (0 << 8)
91 #define TCR_IRGN_WBWA (1 << 8)
92 #define TCR_IRGN_WT (2 << 8)
93 #define TCR_IRGN_WBNWA (3 << 8)
94 #define TCR_IRGN_MASK (3 << 8)
95 #define TCR_ORGN_NC (0 << 10)
96 #define TCR_ORGN_WBWA (1 << 10)
97 #define TCR_ORGN_WT (2 << 10)
98 #define TCR_ORGN_WBNWA (3 << 10)
99 #define TCR_ORGN_MASK (3 << 10)
100 #define TCR_SHARED_NON (0 << 12)
101 #define TCR_SHARED_OUTER (2 << 12)
102 #define TCR_SHARED_INNER (3 << 12)
103 #define TCR_TG0_4K (0 << 14)
104 #define TCR_TG0_64K (1 << 14)
105 #define TCR_TG0_16K (2 << 14)
106 #define TCR_EPD1_DISABLE (1 << 23)
108 #define TCR_EL1_RSVD (1 << 31)
109 #define TCR_EL2_RSVD (1 << 31 | 1 << 23)
110 #define TCR_EL3_RSVD (1 << 31 | 1 << 23)
113 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
115 asm volatile("dsb sy");
117 asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
118 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
119 asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
120 } else if (el == 2) {
121 asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
122 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
123 asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
124 } else if (el == 3) {
125 asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
126 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
127 asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
141 extern struct mm_region *mem_map;
142 void setup_pgtables(void);
143 u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
146 #endif /* _ASM_ARMV8_MMU_H_ */