3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/system.h>
17 * Invalidate L2 Cache using co-proc instruction
19 #ifdef CONFIG_SYS_THUMB_BUILD
20 void invalidate_l2_cache(void);
22 static inline void invalidate_l2_cache(void)
26 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
27 : : "r" (val) : "cc");
32 void l2_cache_enable(void);
33 void l2_cache_disable(void);
34 void set_section_dcache(int section, enum dcache_option option);
36 void arm_init_before_mmu(void);
37 void arm_init_domains(void);
38 void cpu_cache_initialization(void);
39 void dram_bank_mmu_setup(int bank);
44 * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
45 * use that value for aligning DMA buffers unless the board config has specified
46 * an alternate cache line size.
48 #ifdef CONFIG_SYS_CACHELINE_SIZE
49 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
51 #define ARCH_DMA_MINALIGN 64
54 #endif /* _ASM_CACHE_H */