2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __FSL_SECURE_BOOT_H
8 #define __FSL_SECURE_BOOT_H
10 #ifdef CONFIG_SECURE_BOOT
12 #ifndef CONFIG_FIT_SIGNATURE
13 #define CONFIG_CHAIN_OF_TRUST
18 #ifdef CONFIG_CHAIN_OF_TRUST
19 #define CONFIG_CMD_ESBC_VALIDATE
20 #define CONFIG_FSL_SEC_MON
21 #define CONFIG_SHA_HW_ACCEL
22 #define CONFIG_SHA_PROG_HW_ACCEL
23 #define CONFIG_RSA_FREESCALE_EXP
25 #ifndef CONFIG_FSL_CAAM
26 #define CONFIG_FSL_CAAM
29 #define CONFIG_SPL_BOARD_INIT
30 #define CONFIG_SPL_HASH_SUPPORT
31 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
32 #ifdef CONFIG_SPL_BUILD
34 * Define the key hash for U-Boot here if public/private key pair used to
35 * sign U-boot are different from the SRK hash put in the fuse
36 * Example of defining KEY_HASH is
37 * #define CONFIG_SPL_UBOOT_KEY_HASH \
38 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
39 * else leave it defined as NULL
42 #define CONFIG_SPL_UBOOT_KEY_HASH NULL
43 #endif /* ifdef CONFIG_SPL_BUILD */
45 #ifndef CONFIG_SPL_BUILD
46 #define CONFIG_CMD_BLOB
47 #define CONFIG_CMD_HASH
48 #define CONFIG_KEY_REVOCATION
49 #ifndef CONFIG_SYS_RAMBOOT
50 /* The key used for verification of next level images
51 * is picked up from an Extension Table which has
52 * been verified by the ISBC (Internal Secure boot Code)
53 * in boot ROM of the SoC.
54 * The feature is only applicable in case of NOR boot and is
55 * not applicable in case of RAMBOOT (NAND, SD, SPI).
57 #ifndef CONFIG_ESBC_HDR_LS
58 /* Current Key EXT feature not available in LS ESBC Header */
59 #define CONFIG_FSL_ISBC_KEY_EXT
64 #if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A)
65 /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
66 * Similiarly for LS2080
68 #define CONFIG_ESBC_ADDR_64BIT
72 #define CONFIG_EXTRA_ENV \
73 "setenv fdt_high 0xa0000000;" \
74 "setenv initrd_high 0xcfffffff;" \
75 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
77 #define CONFIG_EXTRA_ENV \
78 "setenv fdt_high 0xffffffff;" \
79 "setenv initrd_high 0xffffffff;" \
80 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
83 /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
84 * Non-XIP Memory (Nand/SD)*/
85 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \
86 defined(CONFIG_SD_BOOT)
87 #define CONFIG_BOOTSCRIPT_COPY_RAM
89 /* The address needs to be modified according to NOR, NAND, SD and
93 #define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000
94 #define CONFIG_BS_ADDR_DEVICE 0x583900000
95 #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
96 #define CONFIG_BS_ADDR_RAM 0xa3900000
97 #define CONFIG_BS_HDR_SIZE 0x00002000
98 #define CONFIG_BS_SIZE 0x00001000
100 #ifdef CONFIG_SD_BOOT
101 /* For SD boot address and size are assigned in terms of sector
102 * offset and no. of sectors respectively.
104 #define CONFIG_BS_HDR_ADDR_DEVICE 0x00000800
105 #define CONFIG_BS_ADDR_DEVICE 0x00000840
106 #define CONFIG_BS_HDR_SIZE 0x00000010
107 #define CONFIG_BS_SIZE 0x00000008
109 #define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000
110 #define CONFIG_BS_ADDR_DEVICE 0x60060000
111 #define CONFIG_BS_HDR_SIZE 0x00002000
112 #define CONFIG_BS_SIZE 0x00001000
113 #endif /* #ifdef CONFIG_SD_BOOT */
114 #define CONFIG_BS_HDR_ADDR_RAM 0x81000000
115 #define CONFIG_BS_ADDR_RAM 0x81020000
118 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
119 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
120 #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
122 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE
123 /* BOOTSCRIPT_ADDR is not required */
126 #include <config_fsl_chain_trust.h>
127 #endif /* #ifndef CONFIG_SPL_BUILD */
128 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */