2 * Freescale i.MX28 APBH DMA
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/list.h>
17 #include <linux/compiler.h>
19 #ifndef CONFIG_ARCH_DMA_PIO_WORDS
20 #define DMA_PIO_WORDS 15
22 #define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
25 #define MXS_DMA_ALIGNMENT 32
30 #if defined(CONFIG_MX23)
32 MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
33 MXS_DMA_CHANNEL_AHB_APBH_SSP0,
34 MXS_DMA_CHANNEL_AHB_APBH_SSP1,
35 MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
36 MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
37 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
38 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
39 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
42 #elif defined(CONFIG_MX28)
44 MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
45 MXS_DMA_CHANNEL_AHB_APBH_SSP1,
46 MXS_DMA_CHANNEL_AHB_APBH_SSP2,
47 MXS_DMA_CHANNEL_AHB_APBH_SSP3,
48 MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
49 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
50 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
51 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
52 MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
53 MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
54 MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
55 MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
56 MXS_DMA_CHANNEL_AHB_APBH_HSADC,
57 MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
58 MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
59 MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
62 #elif defined(CONFIG_MX6)
64 MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
65 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
66 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
67 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
68 MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
69 MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
70 MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
71 MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
77 * MXS DMA hardware command.
79 * This structure describes the in-memory layout of an entire DMA command,
80 * including space for the maximum number of PIO accesses. See the appropriate
81 * reference manual for a detailed description of what these fields mean to the
84 #define MXS_DMA_DESC_COMMAND_MASK 0x3
85 #define MXS_DMA_DESC_COMMAND_OFFSET 0
86 #define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
87 #define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
88 #define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
89 #define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
90 #define MXS_DMA_DESC_CHAIN (1 << 2)
91 #define MXS_DMA_DESC_IRQ (1 << 3)
92 #define MXS_DMA_DESC_NAND_LOCK (1 << 4)
93 #define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
94 #define MXS_DMA_DESC_DEC_SEM (1 << 6)
95 #define MXS_DMA_DESC_WAIT4END (1 << 7)
96 #define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
97 #define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
98 #define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
99 #define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
100 #define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
101 #define MXS_DMA_DESC_BYTES_OFFSET 16
108 unsigned long alternate;
110 unsigned long pio_words[DMA_PIO_WORDS];
114 * MXS DMA command descriptor.
116 * This structure incorporates an MXS DMA hardware command structure, along
119 #define MXS_DMA_DESC_FIRST (1 << 0)
120 #define MXS_DMA_DESC_LAST (1 << 1)
121 #define MXS_DMA_DESC_READY (1 << 31)
123 struct mxs_dma_desc {
124 struct mxs_dma_cmd cmd;
128 struct list_head node;
129 } __aligned(MXS_DMA_ALIGNMENT);
134 * This structure represents a single DMA channel. The MXS platform code
135 * maintains an array of these structures to represent every DMA channel in the
136 * system (see mxs_dma_channels).
138 #define MXS_DMA_FLAGS_IDLE 0
139 #define MXS_DMA_FLAGS_BUSY (1 << 0)
140 #define MXS_DMA_FLAGS_FREE 0
141 #define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
142 #define MXS_DMA_FLAGS_VALID (1 << 31)
144 struct mxs_dma_chan {
147 struct mxs_dma_device *dma;
149 unsigned int active_num;
150 unsigned int pending_num;
151 struct list_head active;
152 struct list_head done;
155 struct mxs_dma_desc *mxs_dma_desc_alloc(void);
156 void mxs_dma_desc_free(struct mxs_dma_desc *);
157 int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
159 int mxs_dma_go(int chan);
160 void mxs_dma_init(void);
161 int mxs_dma_init_channel(int chan);
162 int mxs_dma_release(int chan);
164 void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
166 #endif /* __DMA_H__ */