2 * include/asm-arm/macro.h
4 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ASM_ARM_MACRO_H__
10 #define __ASM_ARM_MACRO_H__
14 * These macros provide a convenient way to write 8, 16 and 32 bit data
16 * Registers r4 and r5 are used, any data in these registers are
17 * overwritten by the macros.
18 * The macros are valid for any ARM architecture, they do not implement
19 * any memory barriers so caution is recommended when using these when the
20 * caches are enabled or on a multi-core system.
23 .macro write32, addr, data
29 .macro write16, addr, data
35 .macro write8, addr, data
42 * This macro generates a loop that can be used for delays in the code.
43 * Register r4 is used, any data in this register is overwritten by the
45 * The macro is valid for any ARM architeture. The actual time spent in the
46 * loop will vary from CPU to CPU though.
49 .macro wait_timer, time
64 * Branch according to exception level
66 .macro switch_el, xreg, el3_label, el2_label, el1_label
77 * Branch if current processor is a slave,
78 * choose processor with all zero affinity value as the master.
80 .macro branch_if_slave, xreg, slave_label
82 tst \xreg, #0xff /* Test Affinity 0 */
85 tst \xreg, #0xff /* Test Affinity 1 */
88 tst \xreg, #0xff /* Test Affinity 2 */
91 tst \xreg, #0xff /* Test Affinity 3 */
96 * Branch if current processor is a master,
97 * choose processor with all zero affinity value as the master.
99 .macro branch_if_master, xreg1, xreg2, master_label
100 mrs \xreg1, mpidr_el1
101 lsr \xreg2, \xreg1, #32
102 lsl \xreg1, \xreg1, #40
103 lsr \xreg1, \xreg1, #40
104 orr \xreg1, \xreg1, \xreg2
105 cbz \xreg1, \master_label
108 #endif /* CONFIG_ARM64 */
110 #endif /* __ASSEMBLY__ */
111 #endif /* __ASM_ARM_MACRO_H__ */