1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
5 #include <linux/compiler.h>
6 #include <asm/barriers.h>
11 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
13 #define CR_M (1 << 0) /* MMU enable */
14 #define CR_A (1 << 1) /* Alignment abort enable */
15 #define CR_C (1 << 2) /* Dcache enable */
16 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
17 #define CR_I (1 << 12) /* Icache enable */
18 #define CR_WXN (1 << 19) /* Write Permision Imply XN */
19 #define CR_EE (1 << 25) /* Exception (Big) Endian */
23 u64 get_page_table_size(void);
24 #define PGTABLE_SIZE get_page_table_size()
27 #define MMU_SECTION_SHIFT 21
28 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
30 /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
33 DCACHE_WRITETHROUGH = 3 << 2,
34 DCACHE_WRITEBACK = 4 << 2,
35 DCACHE_WRITEALLOC = 4 << 2,
40 "wfi" : : : "memory"); \
43 static inline unsigned int current_el(void)
46 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
50 static inline unsigned int get_sctlr(void)
56 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
58 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
60 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
65 static inline void set_sctlr(unsigned int val)
71 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
73 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
75 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
80 static inline unsigned long read_mpidr(void)
84 asm volatile("mrs %0, mpidr_el1" : "=r" (val));
91 void __asm_flush_dcache_all(void);
92 void __asm_invalidate_dcache_all(void);
93 void __asm_flush_dcache_range(u64 start, u64 end);
94 void __asm_invalidate_tlb_all(void);
95 void __asm_invalidate_icache_all(void);
96 int __asm_invalidate_l3_dcache(void);
97 int __asm_flush_l3_dcache(void);
98 int __asm_invalidate_l3_icache(void);
99 void __asm_switch_ttbr(u64 new_ttbr);
101 void armv8_switch_to_el2(void);
102 void armv8_switch_to_el1(void);
104 void gic_send_sgi(unsigned long sgino);
105 void wait_for_wakeup(void);
106 void protect_secure_region(void);
107 void smp_kick_all_cpus(void);
109 void flush_l3_cache(void);
112 *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
115 * @args: input and output arguments
118 void smc_call(struct pt_regs *args);
120 void __noreturn psci_system_reset(void);
121 void __noreturn psci_system_off(void);
123 #endif /* __ASSEMBLY__ */
125 #else /* CONFIG_ARM64 */
129 #define CPU_ARCH_UNKNOWN 0
130 #define CPU_ARCH_ARMv3 1
131 #define CPU_ARCH_ARMv4 2
132 #define CPU_ARCH_ARMv4T 3
133 #define CPU_ARCH_ARMv5 4
134 #define CPU_ARCH_ARMv5T 5
135 #define CPU_ARCH_ARMv5TE 6
136 #define CPU_ARCH_ARMv5TEJ 7
137 #define CPU_ARCH_ARMv6 8
138 #define CPU_ARCH_ARMv7 9
141 * CR1 bits (CP#15 CR1)
143 #define CR_M (1 << 0) /* MMU enable */
144 #define CR_A (1 << 1) /* Alignment abort enable */
145 #define CR_C (1 << 2) /* Dcache enable */
146 #define CR_W (1 << 3) /* Write buffer enable */
147 #define CR_P (1 << 4) /* 32-bit exception handler */
148 #define CR_D (1 << 5) /* 32-bit data address range */
149 #define CR_L (1 << 6) /* Implementation defined */
150 #define CR_B (1 << 7) /* Big endian */
151 #define CR_S (1 << 8) /* System MMU protection */
152 #define CR_R (1 << 9) /* ROM MMU protection */
153 #define CR_F (1 << 10) /* Implementation defined */
154 #define CR_Z (1 << 11) /* Implementation defined */
155 #define CR_I (1 << 12) /* Icache enable */
156 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
157 #define CR_RR (1 << 14) /* Round Robin cache replacement */
158 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
159 #define CR_DT (1 << 16)
160 #define CR_IT (1 << 18)
161 #define CR_ST (1 << 19)
162 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
163 #define CR_U (1 << 22) /* Unaligned access operation */
164 #define CR_XP (1 << 23) /* Extended page tables */
165 #define CR_VE (1 << 24) /* Vectored interrupts */
166 #define CR_EE (1 << 25) /* Exception (Big) Endian */
167 #define CR_TRE (1 << 28) /* TEX remap enable */
168 #define CR_AFE (1 << 29) /* Access flag enable */
169 #define CR_TE (1 << 30) /* Thumb exception enable */
171 #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
172 #define PGTABLE_SIZE (4096 * 5)
173 #elif !defined(PGTABLE_SIZE)
174 #define PGTABLE_SIZE (4096 * 4)
178 * This is used to ensure the compiler did actually allocate the register we
179 * asked it for some inline assembly sequences. Apparently we can't trust
180 * the compiler from one version to another so a bit of paranoia won't hurt.
181 * This string is meant to be concatenated with the inline asm string and
182 * will cause compilation to stop on mismatch.
183 * (for details, see gcc PR 15089)
185 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
190 * save_boot_params() - Save boot parameters before starting reset sequence
192 * If you provide this function it will be called immediately U-Boot starts,
193 * both for SPL and U-Boot proper.
195 * All registers are unchanged from U-Boot entry. No registers need be
198 * This is not a normal C function. There is no stack. Return by branching to
199 * save_boot_params_ret.
201 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
205 * save_boot_params_ret() - Return from save_boot_params()
207 * If you provide save_boot_params(), then you should jump back to this
208 * function when done. Try to preserve all registers.
210 * If your implementation of save_boot_params() is in C then it is acceptable
211 * to simply call save_boot_params_ret() at the end of your function. Since
212 * there is no link register set up, you cannot just exit the function. U-Boot
213 * will return to the (initialised) value of lr, and likely crash/hang.
215 * If your implementation of save_boot_params() is in assembler then you
216 * should use 'b' or 'bx' to return to save_boot_params_ret.
218 void save_boot_params_ret(void);
220 #ifdef CONFIG_ARMV7_LPAE
221 void switch_to_hypervisor_ret(void);
224 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
226 #ifdef __ARM_ARCH_7A__
227 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
232 static inline unsigned long get_cpsr(void)
236 asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
240 static inline int is_hyp(void)
242 #ifdef CONFIG_ARMV7_LPAE
243 /* HYP mode requires LPAE ... */
244 return ((get_cpsr() & 0x1f) == 0x1a);
246 /* ... so without LPAE support we can optimize all hyp code away */
251 static inline unsigned int get_cr(void)
256 asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
260 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
266 static inline void set_cr(unsigned int val)
269 asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
273 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
279 static inline unsigned int get_dacr(void)
282 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
286 static inline void set_dacr(unsigned int val)
288 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
289 : : "r" (val) : "cc");
293 #ifdef CONFIG_ARMV7_LPAE
294 /* Long-Descriptor Translation Table Level 1/2 Bits */
295 #define TTB_SECT_XN_MASK (1ULL << 54)
296 #define TTB_SECT_NG_MASK (1 << 11)
297 #define TTB_SECT_AF (1 << 10)
298 #define TTB_SECT_SH_MASK (3 << 8)
299 #define TTB_SECT_NS_MASK (1 << 5)
300 #define TTB_SECT_AP (1 << 6)
301 /* Note: TTB AP bits are set elsewhere */
302 #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
303 #define TTB_SECT (1 << 0)
304 #define TTB_PAGETABLE (3 << 0)
307 #define TTBCR_EAE (1 << 31)
308 #define TTBCR_T0SZ(x) ((x) << 0)
309 #define TTBCR_T1SZ(x) ((x) << 16)
310 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
311 #define TTBCR_IRGN0_NC (0 << 8)
312 #define TTBCR_IRGN0_WBWA (1 << 8)
313 #define TTBCR_IRGN0_WT (2 << 8)
314 #define TTBCR_IRGN0_WBNWA (3 << 8)
315 #define TTBCR_IRGN0_MASK (3 << 8)
316 #define TTBCR_ORGN0_NC (0 << 10)
317 #define TTBCR_ORGN0_WBWA (1 << 10)
318 #define TTBCR_ORGN0_WT (2 << 10)
319 #define TTBCR_ORGN0_WBNWA (3 << 10)
320 #define TTBCR_ORGN0_MASK (3 << 10)
321 #define TTBCR_SHARED_NON (0 << 12)
322 #define TTBCR_SHARED_OUTER (2 << 12)
323 #define TTBCR_SHARED_INNER (3 << 12)
324 #define TTBCR_EPD0 (0 << 7)
329 #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
330 (0xcc << (2 * 8)) | (0xff << (3 * 8)))
332 /* options available for data cache on each page */
334 DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
335 DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
336 DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
337 DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
339 #elif defined(CONFIG_CPU_V7)
340 /* Short-Descriptor Translation Table Level 1 Bits */
341 #define TTB_SECT_NS_MASK (1 << 19)
342 #define TTB_SECT_NG_MASK (1 << 17)
343 #define TTB_SECT_S_MASK (1 << 16)
344 /* Note: TTB AP bits are set elsewhere */
345 #define TTB_SECT_AP (3 << 10)
346 #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
347 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
348 #define TTB_SECT_XN_MASK (1 << 4)
349 #define TTB_SECT_C_MASK (1 << 3)
350 #define TTB_SECT_B_MASK (1 << 2)
351 #define TTB_SECT (2 << 0)
353 /* options available for data cache on each page */
355 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
356 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
357 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
358 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
361 #define TTB_SECT_AP (3 << 10)
362 /* options available for data cache on each page */
365 DCACHE_WRITETHROUGH = 0x1a,
366 DCACHE_WRITEBACK = 0x1e,
367 DCACHE_WRITEALLOC = 0x16,
371 /* Size of an MMU section */
373 #ifdef CONFIG_ARMV7_LPAE
374 MMU_SECTION_SHIFT = 21, /* 2MB */
376 MMU_SECTION_SHIFT = 20, /* 1MB */
378 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
383 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
384 #define TTBR0_RGN_NC (0 << 3)
385 #define TTBR0_RGN_WBWA (1 << 3)
386 #define TTBR0_RGN_WT (2 << 3)
387 #define TTBR0_RGN_WB (3 << 3)
388 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
389 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
390 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
391 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
392 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
396 * Register an update to the page tables, and flush the TLB
398 * \param start start address of update in page table
399 * \param stop stop address of update in page table
401 void mmu_page_table_flush(unsigned long start, unsigned long stop);
403 #endif /* __ASSEMBLY__ */
405 #define arch_align_stack(x) (x)
407 #endif /* __KERNEL__ */
409 #endif /* CONFIG_ARM64 */
413 * Change the cache settings for a region.
415 * \param start start address of memory region to change
416 * \param size size of memory region to change
417 * \param option dcache option to select
419 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
420 enum dcache_option option);
422 #ifdef CONFIG_SYS_NONCACHED_MEMORY
423 void noncached_init(void);
424 phys_addr_t noncached_alloc(size_t size, size_t align);
425 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
427 #endif /* __ASSEMBLY__ */