1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
7 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
9 #define CR_M (1 << 0) /* MMU enable */
10 #define CR_A (1 << 1) /* Alignment abort enable */
11 #define CR_C (1 << 2) /* Dcache enable */
12 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
13 #define CR_I (1 << 12) /* Icache enable */
14 #define CR_WXN (1 << 19) /* Write Permision Imply XN */
15 #define CR_EE (1 << 25) /* Exception (Big) Endian */
17 #ifndef CONFIG_SYS_FULL_VA
18 #define PGTABLE_SIZE (0x10000)
20 #define PGTABLE_SIZE CONFIG_SYS_PGTABLE_SIZE
24 #define MMU_SECTION_SHIFT 21
25 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
35 "isb" : : : "memory"); \
40 "wfi" : : : "memory"); \
43 static inline unsigned int current_el(void)
46 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
50 static inline unsigned int get_sctlr(void)
56 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
58 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
60 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
65 static inline void set_sctlr(unsigned int val)
71 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
73 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
75 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
80 static inline unsigned long read_mpidr(void)
84 asm volatile("mrs %0, mpidr_el1" : "=r" (val));
91 void __asm_flush_dcache_all(void);
92 void __asm_invalidate_dcache_all(void);
93 void __asm_flush_dcache_range(u64 start, u64 end);
94 void __asm_invalidate_tlb_all(void);
95 void __asm_invalidate_icache_all(void);
96 int __asm_flush_l3_cache(void);
98 void armv8_switch_to_el2(void);
99 void armv8_switch_to_el1(void);
101 void gic_send_sgi(unsigned long sgino);
102 void wait_for_wakeup(void);
103 void protect_secure_region(void);
104 void smp_kick_all_cpus(void);
106 void flush_l3_cache(void);
108 #endif /* __ASSEMBLY__ */
110 #else /* CONFIG_ARM64 */
114 #define CPU_ARCH_UNKNOWN 0
115 #define CPU_ARCH_ARMv3 1
116 #define CPU_ARCH_ARMv4 2
117 #define CPU_ARCH_ARMv4T 3
118 #define CPU_ARCH_ARMv5 4
119 #define CPU_ARCH_ARMv5T 5
120 #define CPU_ARCH_ARMv5TE 6
121 #define CPU_ARCH_ARMv5TEJ 7
122 #define CPU_ARCH_ARMv6 8
123 #define CPU_ARCH_ARMv7 9
126 * CR1 bits (CP#15 CR1)
128 #define CR_M (1 << 0) /* MMU enable */
129 #define CR_A (1 << 1) /* Alignment abort enable */
130 #define CR_C (1 << 2) /* Dcache enable */
131 #define CR_W (1 << 3) /* Write buffer enable */
132 #define CR_P (1 << 4) /* 32-bit exception handler */
133 #define CR_D (1 << 5) /* 32-bit data address range */
134 #define CR_L (1 << 6) /* Implementation defined */
135 #define CR_B (1 << 7) /* Big endian */
136 #define CR_S (1 << 8) /* System MMU protection */
137 #define CR_R (1 << 9) /* ROM MMU protection */
138 #define CR_F (1 << 10) /* Implementation defined */
139 #define CR_Z (1 << 11) /* Implementation defined */
140 #define CR_I (1 << 12) /* Icache enable */
141 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
142 #define CR_RR (1 << 14) /* Round Robin cache replacement */
143 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
144 #define CR_DT (1 << 16)
145 #define CR_IT (1 << 18)
146 #define CR_ST (1 << 19)
147 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
148 #define CR_U (1 << 22) /* Unaligned access operation */
149 #define CR_XP (1 << 23) /* Extended page tables */
150 #define CR_VE (1 << 24) /* Vectored interrupts */
151 #define CR_EE (1 << 25) /* Exception (Big) Endian */
152 #define CR_TRE (1 << 28) /* TEX remap enable */
153 #define CR_AFE (1 << 29) /* Access flag enable */
154 #define CR_TE (1 << 30) /* Thumb exception enable */
157 #define PGTABLE_SIZE (4096 * 4)
161 * This is used to ensure the compiler did actually allocate the register we
162 * asked it for some inline assembly sequences. Apparently we can't trust
163 * the compiler from one version to another so a bit of paranoia won't hurt.
164 * This string is meant to be concatenated with the inline asm string and
165 * will cause compilation to stop on mismatch.
166 * (for details, see gcc PR 15089)
168 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
173 * save_boot_params() - Save boot parameters before starting reset sequence
175 * If you provide this function it will be called immediately U-Boot starts,
176 * both for SPL and U-Boot proper.
178 * All registers are unchanged from U-Boot entry. No registers need be
181 * This is not a normal C function. There is no stack. Return by branching to
182 * save_boot_params_ret.
184 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
188 * save_boot_params_ret() - Return from save_boot_params()
190 * If you provide save_boot_params(), then you should jump back to this
191 * function when done. Try to preserve all registers.
193 * If your implementation of save_boot_params() is in C then it is acceptable
194 * to simply call save_boot_params_ret() at the end of your function. Since
195 * there is no link register set up, you cannot just exit the function. U-Boot
196 * will return to the (initialised) value of lr, and likely crash/hang.
198 * If your implementation of save_boot_params() is in assembler then you
199 * should use 'b' or 'bx' to return to save_boot_params_ret.
201 void save_boot_params_ret(void);
203 #define isb() __asm__ __volatile__ ("" : : : "memory")
205 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
207 #ifdef __ARM_ARCH_7A__
208 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
213 static inline unsigned int get_cr(void)
216 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
220 static inline void set_cr(unsigned int val)
222 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
223 : : "r" (val) : "cc");
227 static inline unsigned int get_dacr(void)
230 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
234 static inline void set_dacr(unsigned int val)
236 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
237 : : "r" (val) : "cc");
242 /* Short-Descriptor Translation Table Level 1 Bits */
243 #define TTB_SECT_NS_MASK (1 << 19)
244 #define TTB_SECT_NG_MASK (1 << 17)
245 #define TTB_SECT_S_MASK (1 << 16)
246 /* Note: TTB AP bits are set elsewhere */
247 #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
248 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
249 #define TTB_SECT_XN_MASK (1 << 4)
250 #define TTB_SECT_C_MASK (1 << 3)
251 #define TTB_SECT_B_MASK (1 << 2)
252 #define TTB_SECT (2 << 0)
254 /* options available for data cache on each page */
256 DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
257 TTB_SECT_XN_MASK | TTB_SECT,
258 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
259 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
260 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
263 /* options available for data cache on each page */
266 DCACHE_WRITETHROUGH = 0x1a,
267 DCACHE_WRITEBACK = 0x1e,
268 DCACHE_WRITEALLOC = 0x16,
272 /* Size of an MMU section */
274 MMU_SECTION_SHIFT = 20,
275 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
280 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
281 #define TTBR0_RGN_NC (0 << 3)
282 #define TTBR0_RGN_WBWA (1 << 3)
283 #define TTBR0_RGN_WT (2 << 3)
284 #define TTBR0_RGN_WB (3 << 3)
285 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
286 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
287 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
288 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
289 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
293 * Register an update to the page tables, and flush the TLB
295 * \param start start address of update in page table
296 * \param stop stop address of update in page table
298 void mmu_page_table_flush(unsigned long start, unsigned long stop);
300 #endif /* __ASSEMBLY__ */
302 #define arch_align_stack(x) (x)
304 #endif /* __KERNEL__ */
306 #endif /* CONFIG_ARM64 */
310 * Change the cache settings for a region.
312 * \param start start address of memory region to change
313 * \param size size of memory region to change
314 * \param option dcache option to select
316 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
317 enum dcache_option option);
319 #ifdef CONFIG_SYS_NONCACHED_MEMORY
320 void noncached_init(void);
321 phys_addr_t noncached_alloc(size_t size, size_t align);
322 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
324 #endif /* __ASSEMBLY__ */