3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/cache.h>
11 #include <linux/compiler.h>
13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
15 DECLARE_GLOBAL_DATA_PTR;
17 __weak void arm_init_before_mmu(void)
21 __weak void arm_init_domains(void)
25 static void cp_delay (void)
29 /* copro seems to need some delay between reading and writing */
30 for (i = 0; i < 100; i++)
32 asm volatile("" : : : "memory");
35 void set_section_dcache(int section, enum dcache_option option)
37 #ifdef CONFIG_ARMV7_LPAE
38 u64 *page_table = (u64 *)gd->arch.tlb_addr;
39 /* Need to set the access flag to not fault */
40 u64 value = TTB_SECT_AP | TTB_SECT_AF;
42 u32 *page_table = (u32 *)gd->arch.tlb_addr;
43 u32 value = TTB_SECT_AP;
46 /* Add the page offset */
47 value |= ((u32)section << MMU_SECTION_SHIFT);
49 /* Add caching bits */
53 page_table[section] = value;
56 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
58 debug("%s: Warning: not implemented\n", __func__);
61 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
62 enum dcache_option option)
64 u32 *page_table = (u32 *)gd->arch.tlb_addr;
65 unsigned long upto, end;
67 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
68 start = start >> MMU_SECTION_SHIFT;
69 debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
71 for (upto = start; upto < end; upto++)
72 set_section_dcache(upto, option);
73 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
76 __weak void dram_bank_mmu_setup(int bank)
81 debug("%s: bank: %d\n", __func__, bank);
82 for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
83 i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
84 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
86 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
87 set_section_dcache(i, DCACHE_WRITETHROUGH);
88 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
89 set_section_dcache(i, DCACHE_WRITEALLOC);
91 set_section_dcache(i, DCACHE_WRITEBACK);
96 /* to activate the MMU we need to set up virtual memory: use 1M areas */
97 static inline void mmu_setup(void)
102 arm_init_before_mmu();
103 /* Set up an identity-mapping for all 4GB, rw for everyone */
104 for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
105 set_section_dcache(i, DCACHE_OFF);
107 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
108 dram_bank_mmu_setup(i);
111 #ifdef CONFIG_ARMV7_LPAE
112 /* Set up 4 PTE entries pointing to our 4 1GB page tables */
113 for (i = 0; i < 4; i++) {
114 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
115 u64 tpt = gd->arch.tlb_addr + (4096 * i);
116 page_table[i] = tpt | TTB_PAGETABLE;
120 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
121 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
122 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
123 reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
125 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
129 /* Set HCTR to enable LPAE */
130 asm volatile("mcr p15, 4, %0, c2, c0, 2"
131 : : "r" (reg) : "memory");
133 asm volatile("mcrr p15, 4, %0, %1, c2"
135 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
138 asm volatile("mcr p15, 4, %0, c10, c2, 0"
139 : : "r" (MEMORY_ATTRIBUTES) : "memory");
141 /* Set TTBCR to enable LPAE */
142 asm volatile("mcr p15, 0, %0, c2, c0, 2"
143 : : "r" (reg) : "memory");
144 /* Set 64-bit TTBR0 */
145 asm volatile("mcrr p15, 0, %0, %1, c2"
147 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
150 asm volatile("mcr p15, 0, %0, c10, c2, 0"
151 : : "r" (MEMORY_ATTRIBUTES) : "memory");
153 #elif defined(CONFIG_CPU_V7)
155 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
156 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
157 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
158 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
159 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
161 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
163 asm volatile("mcr p15, 0, %0, c2, c0, 0"
164 : : "r" (reg) : "memory");
166 /* Copy the page table address to cp15 */
167 asm volatile("mcr p15, 0, %0, c2, c0, 0"
168 : : "r" (gd->arch.tlb_addr) : "memory");
170 /* Set the access control to all-supervisor */
171 asm volatile("mcr p15, 0, %0, c3, c0, 0"
176 /* and enable the mmu */
177 reg = get_cr(); /* get control reg. */
182 static int mmu_enabled(void)
184 return get_cr() & CR_M;
187 /* cache_bit must be either CR_I or CR_C */
188 static void cache_enable(uint32_t cache_bit)
192 /* The data cache is not active unless the mmu is enabled too */
193 if ((cache_bit == CR_C) && !mmu_enabled())
195 reg = get_cr(); /* get control reg. */
197 set_cr(reg | cache_bit);
200 /* cache_bit must be either CR_I or CR_C */
201 static void cache_disable(uint32_t cache_bit)
208 if (cache_bit == CR_C) {
209 /* if cache isn;t enabled no need to disable */
210 if ((reg & CR_C) != CR_C)
212 /* if disabling data cache, disable mmu too */
217 if (cache_bit == (CR_C | CR_M))
219 set_cr(reg & ~cache_bit);
223 #ifdef CONFIG_SYS_ICACHE_OFF
224 void icache_enable (void)
229 void icache_disable (void)
234 int icache_status (void)
236 return 0; /* always off */
239 void icache_enable(void)
244 void icache_disable(void)
249 int icache_status(void)
251 return (get_cr() & CR_I) != 0;
255 #ifdef CONFIG_SYS_DCACHE_OFF
256 void dcache_enable (void)
261 void dcache_disable (void)
266 int dcache_status (void)
268 return 0; /* always off */
271 void dcache_enable(void)
276 void dcache_disable(void)
281 int dcache_status(void)
283 return (get_cr() & CR_C) != 0;