3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/cache.h>
11 #include <linux/compiler.h>
13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
15 DECLARE_GLOBAL_DATA_PTR;
17 void __arm_init_before_mmu(void)
20 void arm_init_before_mmu(void)
21 __attribute__((weak, alias("__arm_init_before_mmu")));
23 __weak void arm_init_domains(void)
27 static void cp_delay (void)
31 /* copro seems to need some delay between reading and writing */
32 for (i = 0; i < 100; i++)
34 asm volatile("" : : : "memory");
37 void set_section_dcache(int section, enum dcache_option option)
39 u32 *page_table = (u32 *)gd->arch.tlb_addr;
42 value = (section << MMU_SECTION_SHIFT) | (3 << 10);
44 page_table[section] = value;
47 void __mmu_page_table_flush(unsigned long start, unsigned long stop)
49 debug("%s: Warning: not implemented\n", __func__);
52 void mmu_page_table_flush(unsigned long start, unsigned long stop)
53 __attribute__((weak, alias("__mmu_page_table_flush")));
55 void mmu_set_region_dcache_behaviour(u32 start, int size,
56 enum dcache_option option)
58 u32 *page_table = (u32 *)gd->arch.tlb_addr;
61 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
62 start = start >> MMU_SECTION_SHIFT;
63 debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
65 for (upto = start; upto < end; upto++)
66 set_section_dcache(upto, option);
67 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
70 __weak void dram_bank_mmu_setup(int bank)
75 debug("%s: bank: %d\n", __func__, bank);
76 for (i = bd->bi_dram[bank].start >> 20;
77 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
79 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
80 set_section_dcache(i, DCACHE_WRITETHROUGH);
82 set_section_dcache(i, DCACHE_WRITEBACK);
87 /* to activate the MMU we need to set up virtual memory: use 1M areas */
88 static inline void mmu_setup(void)
93 arm_init_before_mmu();
94 /* Set up an identity-mapping for all 4GB, rw for everyone */
95 for (i = 0; i < 4096; i++)
96 set_section_dcache(i, DCACHE_OFF);
98 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
99 dram_bank_mmu_setup(i);
102 /* Copy the page table address to cp15 */
103 asm volatile("mcr p15, 0, %0, c2, c0, 0"
104 : : "r" (gd->arch.tlb_addr) : "memory");
105 /* Set the access control to all-supervisor */
106 asm volatile("mcr p15, 0, %0, c3, c0, 0"
111 /* and enable the mmu */
112 reg = get_cr(); /* get control reg. */
117 static int mmu_enabled(void)
119 return get_cr() & CR_M;
122 /* cache_bit must be either CR_I or CR_C */
123 static void cache_enable(uint32_t cache_bit)
127 /* The data cache is not active unless the mmu is enabled too */
128 if ((cache_bit == CR_C) && !mmu_enabled())
130 reg = get_cr(); /* get control reg. */
132 set_cr(reg | cache_bit);
135 /* cache_bit must be either CR_I or CR_C */
136 static void cache_disable(uint32_t cache_bit)
143 if (cache_bit == CR_C) {
144 /* if cache isn;t enabled no need to disable */
145 if ((reg & CR_C) != CR_C)
147 /* if disabling data cache, disable mmu too */
152 if (cache_bit == (CR_C | CR_M))
154 set_cr(reg & ~cache_bit);
158 #ifdef CONFIG_SYS_ICACHE_OFF
159 void icache_enable (void)
164 void icache_disable (void)
169 int icache_status (void)
171 return 0; /* always off */
174 void icache_enable(void)
179 void icache_disable(void)
184 int icache_status(void)
186 return (get_cr() & CR_I) != 0;
190 #ifdef CONFIG_SYS_DCACHE_OFF
191 void dcache_enable (void)
196 void dcache_disable (void)
201 int dcache_status (void)
203 return 0; /* always off */
206 void dcache_enable(void)
211 void dcache_disable(void)
216 int dcache_status(void)
218 return (get_cr() & CR_C) != 0;