3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/cache.h>
11 #include <linux/compiler.h>
13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
15 DECLARE_GLOBAL_DATA_PTR;
17 __weak void arm_init_before_mmu(void)
21 __weak void arm_init_domains(void)
25 static void cp_delay (void)
29 /* copro seems to need some delay between reading and writing */
30 for (i = 0; i < 100; i++)
32 asm volatile("" : : : "memory");
35 void set_section_dcache(int section, enum dcache_option option)
37 #ifdef CONFIG_ARMV7_LPAE
38 u64 *page_table = (u64 *)gd->arch.tlb_addr;
39 /* Need to set the access flag to not fault */
40 u64 value = TTB_SECT_AP | TTB_SECT_AF;
42 u32 *page_table = (u32 *)gd->arch.tlb_addr;
43 u32 value = TTB_SECT_AP;
46 /* Add the page offset */
47 value |= ((u32)section << MMU_SECTION_SHIFT);
49 /* Add caching bits */
53 page_table[section] = value;
56 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
58 debug("%s: Warning: not implemented\n", __func__);
61 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
62 enum dcache_option option)
64 #ifdef CONFIG_ARMV7_LPAE
65 u64 *page_table = (u64 *)gd->arch.tlb_addr;
67 u32 *page_table = (u32 *)gd->arch.tlb_addr;
69 unsigned long startpt, stoppt;
70 unsigned long upto, end;
72 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
73 start = start >> MMU_SECTION_SHIFT;
74 #ifdef CONFIG_ARMV7_LPAE
75 debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
78 debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
81 for (upto = start; upto < end; upto++)
82 set_section_dcache(upto, option);
85 * Make sure range is cache line aligned
86 * Only CPU maintains page tables, hence it is safe to always
87 * flush complete cache lines...
90 startpt = (unsigned long)&page_table[start];
91 startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
92 stoppt = (unsigned long)&page_table[end];
93 stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
94 mmu_page_table_flush(startpt, stoppt);
97 __weak void dram_bank_mmu_setup(int bank)
102 debug("%s: bank: %d\n", __func__, bank);
103 for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
104 i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
105 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
107 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
108 set_section_dcache(i, DCACHE_WRITETHROUGH);
109 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
110 set_section_dcache(i, DCACHE_WRITEALLOC);
112 set_section_dcache(i, DCACHE_WRITEBACK);
117 /* to activate the MMU we need to set up virtual memory: use 1M areas */
118 static inline void mmu_setup(void)
123 arm_init_before_mmu();
124 /* Set up an identity-mapping for all 4GB, rw for everyone */
125 for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
126 set_section_dcache(i, DCACHE_OFF);
128 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
129 dram_bank_mmu_setup(i);
132 #ifdef CONFIG_ARMV7_LPAE
133 /* Set up 4 PTE entries pointing to our 4 1GB page tables */
134 for (i = 0; i < 4; i++) {
135 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
136 u64 tpt = gd->arch.tlb_addr + (4096 * i);
137 page_table[i] = tpt | TTB_PAGETABLE;
141 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
142 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
143 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
144 reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
146 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
150 /* Set HCTR to enable LPAE */
151 asm volatile("mcr p15, 4, %0, c2, c0, 2"
152 : : "r" (reg) : "memory");
154 asm volatile("mcrr p15, 4, %0, %1, c2"
156 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
159 asm volatile("mcr p15, 4, %0, c10, c2, 0"
160 : : "r" (MEMORY_ATTRIBUTES) : "memory");
162 /* Set TTBCR to enable LPAE */
163 asm volatile("mcr p15, 0, %0, c2, c0, 2"
164 : : "r" (reg) : "memory");
165 /* Set 64-bit TTBR0 */
166 asm volatile("mcrr p15, 0, %0, %1, c2"
168 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
171 asm volatile("mcr p15, 0, %0, c10, c2, 0"
172 : : "r" (MEMORY_ATTRIBUTES) : "memory");
174 #elif defined(CONFIG_CPU_V7)
176 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
177 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
178 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
179 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
180 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
182 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
184 asm volatile("mcr p15, 0, %0, c2, c0, 0"
185 : : "r" (reg) : "memory");
187 /* Copy the page table address to cp15 */
188 asm volatile("mcr p15, 0, %0, c2, c0, 0"
189 : : "r" (gd->arch.tlb_addr) : "memory");
191 /* Set the access control to all-supervisor */
192 asm volatile("mcr p15, 0, %0, c3, c0, 0"
197 /* and enable the mmu */
198 reg = get_cr(); /* get control reg. */
203 static int mmu_enabled(void)
205 return get_cr() & CR_M;
208 /* cache_bit must be either CR_I or CR_C */
209 static void cache_enable(uint32_t cache_bit)
213 /* The data cache is not active unless the mmu is enabled too */
214 if ((cache_bit == CR_C) && !mmu_enabled())
216 reg = get_cr(); /* get control reg. */
218 set_cr(reg | cache_bit);
221 /* cache_bit must be either CR_I or CR_C */
222 static void cache_disable(uint32_t cache_bit)
229 if (cache_bit == CR_C) {
230 /* if cache isn;t enabled no need to disable */
231 if ((reg & CR_C) != CR_C)
233 /* if disabling data cache, disable mmu too */
238 if (cache_bit == (CR_C | CR_M))
240 set_cr(reg & ~cache_bit);
244 #ifdef CONFIG_SYS_ICACHE_OFF
245 void icache_enable (void)
250 void icache_disable (void)
255 int icache_status (void)
257 return 0; /* always off */
260 void icache_enable(void)
265 void icache_disable(void)
270 int icache_status(void)
272 return (get_cr() & CR_I) != 0;
276 #ifdef CONFIG_SYS_DCACHE_OFF
277 void dcache_enable (void)
282 void dcache_disable (void)
287 int dcache_status (void)
289 return 0; /* always off */
292 void dcache_enable(void)
297 void dcache_disable(void)
302 int dcache_status(void)
304 return (get_cr() & CR_C) != 0;