3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/cache.h>
11 #include <linux/compiler.h>
13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
15 DECLARE_GLOBAL_DATA_PTR;
17 __weak void arm_init_before_mmu(void)
21 __weak void arm_init_domains(void)
25 void set_section_dcache(int section, enum dcache_option option)
27 #ifdef CONFIG_ARMV7_LPAE
28 u64 *page_table = (u64 *)gd->arch.tlb_addr;
29 /* Need to set the access flag to not fault */
30 u64 value = TTB_SECT_AP | TTB_SECT_AF;
32 u32 *page_table = (u32 *)gd->arch.tlb_addr;
33 u32 value = TTB_SECT_AP;
36 /* Add the page offset */
37 value |= ((u32)section << MMU_SECTION_SHIFT);
39 /* Add caching bits */
43 page_table[section] = value;
46 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
48 debug("%s: Warning: not implemented\n", __func__);
51 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
52 enum dcache_option option)
54 #ifdef CONFIG_ARMV7_LPAE
55 u64 *page_table = (u64 *)gd->arch.tlb_addr;
57 u32 *page_table = (u32 *)gd->arch.tlb_addr;
59 unsigned long startpt, stoppt;
60 unsigned long upto, end;
62 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
63 start = start >> MMU_SECTION_SHIFT;
64 #ifdef CONFIG_ARMV7_LPAE
65 debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
68 debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
71 for (upto = start; upto < end; upto++)
72 set_section_dcache(upto, option);
75 * Make sure range is cache line aligned
76 * Only CPU maintains page tables, hence it is safe to always
77 * flush complete cache lines...
80 startpt = (unsigned long)&page_table[start];
81 startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
82 stoppt = (unsigned long)&page_table[end];
83 stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
84 mmu_page_table_flush(startpt, stoppt);
87 __weak void dram_bank_mmu_setup(int bank)
92 debug("%s: bank: %d\n", __func__, bank);
93 for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
94 i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
95 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
97 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
98 set_section_dcache(i, DCACHE_WRITETHROUGH);
99 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
100 set_section_dcache(i, DCACHE_WRITEALLOC);
102 set_section_dcache(i, DCACHE_WRITEBACK);
107 /* to activate the MMU we need to set up virtual memory: use 1M areas */
108 static inline void mmu_setup(void)
113 arm_init_before_mmu();
114 /* Set up an identity-mapping for all 4GB, rw for everyone */
115 for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
116 set_section_dcache(i, DCACHE_OFF);
118 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
119 dram_bank_mmu_setup(i);
122 #if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
123 /* Set up 4 PTE entries pointing to our 4 1GB page tables */
124 for (i = 0; i < 4; i++) {
125 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
126 u64 tpt = gd->arch.tlb_addr + (4096 * i);
127 page_table[i] = tpt | TTB_PAGETABLE;
131 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
132 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
133 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
134 reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
136 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
140 /* Set HTCR to enable LPAE */
141 asm volatile("mcr p15, 4, %0, c2, c0, 2"
142 : : "r" (reg) : "memory");
144 asm volatile("mcrr p15, 4, %0, %1, c2"
146 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
149 asm volatile("mcr p15, 4, %0, c10, c2, 0"
150 : : "r" (MEMORY_ATTRIBUTES) : "memory");
152 /* Set TTBCR to enable LPAE */
153 asm volatile("mcr p15, 0, %0, c2, c0, 2"
154 : : "r" (reg) : "memory");
155 /* Set 64-bit TTBR0 */
156 asm volatile("mcrr p15, 0, %0, %1, c2"
158 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
161 asm volatile("mcr p15, 0, %0, c10, c2, 0"
162 : : "r" (MEMORY_ATTRIBUTES) : "memory");
164 #elif defined(CONFIG_CPU_V7)
166 /* Set HTCR to disable LPAE */
167 asm volatile("mcr p15, 4, %0, c2, c0, 2"
168 : : "r" (0) : "memory");
170 /* Set TTBCR to disable LPAE */
171 asm volatile("mcr p15, 0, %0, c2, c0, 2"
172 : : "r" (0) : "memory");
175 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
176 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
177 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
178 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
179 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
181 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
183 asm volatile("mcr p15, 0, %0, c2, c0, 0"
184 : : "r" (reg) : "memory");
186 /* Copy the page table address to cp15 */
187 asm volatile("mcr p15, 0, %0, c2, c0, 0"
188 : : "r" (gd->arch.tlb_addr) : "memory");
190 /* Set the access control to all-supervisor */
191 asm volatile("mcr p15, 0, %0, c3, c0, 0"
196 /* and enable the mmu */
197 reg = get_cr(); /* get control reg. */
201 static int mmu_enabled(void)
203 return get_cr() & CR_M;
206 /* cache_bit must be either CR_I or CR_C */
207 static void cache_enable(uint32_t cache_bit)
211 /* The data cache is not active unless the mmu is enabled too */
212 if ((cache_bit == CR_C) && !mmu_enabled())
214 reg = get_cr(); /* get control reg. */
215 set_cr(reg | cache_bit);
218 /* cache_bit must be either CR_I or CR_C */
219 static void cache_disable(uint32_t cache_bit)
225 if (cache_bit == CR_C) {
226 /* if cache isn;t enabled no need to disable */
227 if ((reg & CR_C) != CR_C)
229 /* if disabling data cache, disable mmu too */
234 if (cache_bit == (CR_C | CR_M))
236 set_cr(reg & ~cache_bit);
240 #ifdef CONFIG_SYS_ICACHE_OFF
241 void icache_enable (void)
246 void icache_disable (void)
251 int icache_status (void)
253 return 0; /* always off */
256 void icache_enable(void)
261 void icache_disable(void)
266 int icache_status(void)
268 return (get_cr() & CR_I) != 0;
272 #ifdef CONFIG_SYS_DCACHE_OFF
273 void dcache_enable (void)
278 void dcache_disable (void)
283 int dcache_status (void)
285 return 0; /* always off */
288 void dcache_enable(void)
293 void dcache_disable(void)
298 int dcache_status(void)
300 return (get_cr() & CR_C) != 0;