3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/system.h>
27 #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
29 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
30 #define CACHE_SETUP 0x1a
32 #define CACHE_SETUP 0x1e
35 DECLARE_GLOBAL_DATA_PTR;
37 static void cp_delay (void)
41 /* copro seems to need some delay between reading and writing */
42 for (i = 0; i < 100; i++)
44 asm volatile("" : : : "memory");
47 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
48 static inline void dram_bank_mmu_setup(int bank)
50 u32 *page_table = (u32 *)gd->tlb_addr;
54 debug("%s: bank: %d\n", __func__, bank);
55 for (i = bd->bi_dram[bank].start >> 20;
56 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
58 page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
63 /* to activate the MMU we need to set up virtual memory: use 1M areas */
64 static inline void mmu_setup(void)
66 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
67 u32 *page_table = (u32 *)gd->tlb_addr;
69 static u32 __attribute__((aligned(16384))) page_table[4096];
76 /* Set up an identity-mapping for all 4GB, rw for everyone */
77 for (i = 0; i < 4096; i++)
78 page_table[i] = i << 20 | (3 << 10) | 0x12;
80 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
81 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
82 dram_bank_mmu_setup(i);
85 /* Then, enable cacheable and bufferable for RAM only */
86 for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) {
87 for (i = bd->bi_dram[j].start >> 20;
88 i < (bd->bi_dram[j].start + bd->bi_dram[j].size) >> 20;
90 page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
95 /* Copy the page table address to cp15 */
96 asm volatile("mcr p15, 0, %0, c2, c0, 0"
97 : : "r" (page_table) : "memory");
98 /* Set the access control to all-supervisor */
99 asm volatile("mcr p15, 0, %0, c3, c0, 0"
101 /* and enable the mmu */
102 reg = get_cr(); /* get control reg. */
107 /* cache_bit must be either CR_I or CR_C */
108 static void cache_enable(uint32_t cache_bit)
112 /* The data cache is not active unless the mmu is enabled too */
113 if (cache_bit == CR_C)
115 reg = get_cr(); /* get control reg. */
117 set_cr(reg | cache_bit);
120 /* cache_bit must be either CR_I or CR_C */
121 static void cache_disable(uint32_t cache_bit)
125 if (cache_bit == CR_C) {
126 /* if cache isn;t enabled no need to disable */
128 if ((reg & CR_C) != CR_C)
130 /* if disabling data cache, disable mmu too */
136 set_cr(reg & ~cache_bit);
140 #ifdef CONFIG_SYS_NO_ICACHE
141 void icache_enable (void)
146 void icache_disable (void)
151 int icache_status (void)
153 return 0; /* always off */
156 void icache_enable(void)
161 void icache_disable(void)
166 int icache_status(void)
168 return (get_cr() & CR_I) != 0;
172 #ifdef CONFIG_SYS_NO_DCACHE
173 void dcache_enable (void)
178 void dcache_disable (void)
183 int dcache_status (void)
185 return 0; /* always off */
188 void dcache_enable(void)
193 void dcache_disable(void)
198 int dcache_status(void)
200 return (get_cr() & CR_C) != 0;