2 * GIC Initialization Routines.
5 * David Feng <fenghua@phytium.com.cn>
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm-offsets.h>
12 #include <linux/linkage.h>
14 #include <asm/macro.h>
17 /*************************************************************************
19 * void gic_init_secure(DistributorBase);
21 * Initialize secure copy of GIC at EL3.
23 *************************************************************************/
24 ENTRY(gic_init_secure)
26 * Initialize Distributor
27 * x0: Distributor Base
29 #if defined(CONFIG_GICV3)
30 mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */
31 /* EnableGrp1S | ARE_S | ARE_NS */
32 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
33 ldr w9, [x0, GICD_TYPER]
34 and w10, w9, #0x1f /* ITLinesNumber */
35 cbz w10, 1f /* No SPIs */
36 add x11, x0, (GICD_IGROUPRn + 4)
37 add x12, x0, (GICD_IGROUPMODRn + 4)
39 0: str w9, [x11], #0x4
40 str wzr, [x12], #0x4 /* Config SPIs as Group1NS */
43 #elif defined(CONFIG_GICV2)
44 mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */
45 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
46 ldr w9, [x0, GICD_TYPER]
47 and w10, w9, #0x1f /* ITLinesNumber */
48 cbz w10, 1f /* No SPIs */
49 add x11, x0, (GICD_IGROUPRn + 4)
50 mov w9, #~0 /* Config SPIs as Grp1 */
51 0: str w9, [x11], #0x4
57 ENDPROC(gic_init_secure)
60 /*************************************************************************
62 * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase);
64 * void gic_init_secure_percpu(ReDistributorBase);
66 * Initialize secure copy of GIC at EL3.
68 *************************************************************************/
69 ENTRY(gic_init_secure_percpu)
70 #if defined(CONFIG_GICV3)
72 * Initialize ReDistributor
73 * x0: ReDistributor Base
77 bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */
79 1: ldr x11, [x9, GICR_TYPER]
80 lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */
83 add x9, x9, #(2 << 16)
86 /* x9: ReDistributor Base Address of Current CPU */
88 ldr w11, [x9, GICR_WAKER]
89 and w11, w11, w10 /* Clear ProcessorSleep */
90 str w11, [x9, GICR_WAKER]
93 3: ldr w10, [x9, GICR_WAKER]
94 tbnz w10, #2, 3b /* Wait Children be Alive */
96 add x10, x9, #(1 << 16) /* SGI_Base */
98 str w11, [x10, GICR_IGROUPRn]
99 str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
100 mov w11, #0x1 /* Enable SGI 0 */
101 str w11, [x10, GICR_ISENABLERn]
103 /* Initialize Cpu Interface */
105 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
106 /* Allow EL2 access to ICC_SRE_EL2 */
111 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
112 /* Allow EL1 access to ICC_SRE_EL1 */
116 mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
117 msr ICC_IGRPEN1_EL3, x10
120 msr ICC_CTLR_EL3, xzr
123 msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
126 mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */
129 #elif defined(CONFIG_GICV2)
131 * Initialize SGIs and PPIs
132 * x0: Distributor Base
133 * x1: Cpu Interface Base
135 mov w9, #~0 /* Config SGIs and PPIs as Grp1 */
136 str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */
137 mov w9, #0x1 /* Enable SGI 0 */
138 str w9, [x0, GICD_ISENABLERn]
140 /* Initialize Cpu Interface */
141 mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */
142 /* Enable Ack Group1 Interrupt & */
143 /* EnableGrp0 & EnableGrp1 */
144 str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */
146 mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */
147 str w9, [x1, GICC_PMR]
150 ENDPROC(gic_init_secure_percpu)
153 /*************************************************************************
155 * void gic_kick_secondary_cpus(DistributorBase);
157 * void gic_kick_secondary_cpus(void);
159 *************************************************************************/
160 ENTRY(gic_kick_secondary_cpus)
161 #if defined(CONFIG_GICV3)
163 msr ICC_ASGI1R_EL1, x9
165 #elif defined(CONFIG_GICV2)
167 movk w9, #0x100, lsl #16
168 str w9, [x0, GICD_SGIR]
171 ENDPROC(gic_kick_secondary_cpus)
174 /*************************************************************************
176 * void gic_wait_for_interrupt(CpuInterfaceBase);
178 * void gic_wait_for_interrupt(void);
180 * Wait for SGI 0 from master.
182 *************************************************************************/
183 ENTRY(gic_wait_for_interrupt)
184 #if defined(CONFIG_GICV3)
185 gic_wait_for_interrupt_m x9
186 #elif defined(CONFIG_GICV2)
187 gic_wait_for_interrupt_m x0, w9
190 ENDPROC(gic_wait_for_interrupt)