2 * Copyright (c) 2016 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/timer.h>
12 #include <asm/arch/wdt.h>
13 #include <linux/err.h>
14 #include <dm/uclass.h>
17 * Second Watchdog Timer by default is configured
18 * to trigger secondary boot source.
20 #define AST_2ND_BOOT_WDT 1
23 * Third Watchdog Timer by default is configured
24 * to toggle Flash address mode switch before reset.
26 #define AST_FLASH_ADDR_DETECT_WDT 2
28 DECLARE_GLOBAL_DATA_PTR;
30 void lowlevel_init(void)
33 * These two watchdogs need to be stopped as soon as possible,
34 * otherwise the board might hang. By default they are set to
35 * a very short timeout and even simple debug write to serial
36 * console early in the init process might cause them to fire.
38 struct ast_wdt *flash_addr_wdt =
39 (struct ast_wdt *)(WDT_BASE +
40 sizeof(struct ast_wdt) *
41 AST_FLASH_ADDR_DETECT_WDT);
43 clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN);
45 #ifndef CONFIG_FIRMWARE_2ND_BOOT
46 struct ast_wdt *sec_boot_wdt =
47 (struct ast_wdt *)(WDT_BASE +
48 sizeof(struct ast_wdt) *
51 clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN);
57 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
68 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
70 debug("DRAM FAIL1\r\n");
74 ret = ram_get_info(dev, &ram);
76 debug("DRAM FAIL2\r\n");
80 gd->ram_size = ram.size;