1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Google, Inc
10 #include <asm/arch/timer.h>
11 #include <asm/arch/wdt.h>
12 #include <linux/err.h>
13 #include <dm/uclass.h>
16 * Second Watchdog Timer by default is configured
17 * to trigger secondary boot source.
19 #define AST_2ND_BOOT_WDT 1
22 * Third Watchdog Timer by default is configured
23 * to toggle Flash address mode switch before reset.
25 #define AST_FLASH_ADDR_DETECT_WDT 2
27 DECLARE_GLOBAL_DATA_PTR;
29 void lowlevel_init(void)
32 * These two watchdogs need to be stopped as soon as possible,
33 * otherwise the board might hang. By default they are set to
34 * a very short timeout and even simple debug write to serial
35 * console early in the init process might cause them to fire.
37 struct ast_wdt *flash_addr_wdt =
38 (struct ast_wdt *)(WDT_BASE +
39 sizeof(struct ast_wdt) *
40 AST_FLASH_ADDR_DETECT_WDT);
42 clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN);
44 #ifndef CONFIG_FIRMWARE_2ND_BOOT
45 struct ast_wdt *sec_boot_wdt =
46 (struct ast_wdt *)(WDT_BASE +
47 sizeof(struct ast_wdt) *
50 clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN);
56 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
67 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
69 debug("DRAM FAIL1\r\n");
73 ret = ram_get_info(dev, &ram);
75 debug("DRAM FAIL2\r\n");
79 gd->ram_size = ram.size;