2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/at91_pit.h>
13 #include <asm/arch/clk.h>
16 #if !defined(CONFIG_AT91FAMILY)
17 # error You need to define CONFIG_AT91FAMILY in your board config!
20 DECLARE_GLOBAL_DATA_PTR;
23 * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
24 * setting the 20 bit counter period to its maximum (0xfffff).
25 * (See the relevant data sheets to understand that this really works)
27 * We do also mimic the typical powerpc way of incrementing
28 * two 32 bit registers called tbl and tbu.
30 * Those registers increment at 1/16 the main clock rate.
33 #define TIMER_LOAD_VAL 0xfffff
36 * Use the PITC in full 32 bit incrementing mode
40 at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
42 at91_periph_clk_enable(ATMEL_ID_SYS);
45 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
47 gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
53 * Return the number of timer ticks per second.
57 return gd->arch.timer_rate_hz;