1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/at91_pit.h>
12 #include <asm/arch/clk.h>
15 #if !defined(CONFIG_AT91FAMILY)
16 # error You need to define CONFIG_AT91FAMILY in your board config!
19 DECLARE_GLOBAL_DATA_PTR;
22 * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
23 * setting the 20 bit counter period to its maximum (0xfffff).
24 * (See the relevant data sheets to understand that this really works)
26 * We do also mimic the typical powerpc way of incrementing
27 * two 32 bit registers called tbl and tbu.
29 * Those registers increment at 1/16 the main clock rate.
32 #define TIMER_LOAD_VAL 0xfffff
35 * Use the PITC in full 32 bit incrementing mode
39 at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
41 at91_periph_clk_enable(ATMEL_ID_SYS);
44 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
46 gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
52 * Return the number of timer ticks per second.
56 return gd->arch.timer_rate_hz;