1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
8 * Bo Shen <voice.shen@atmel.com>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/at91_pit.h>
15 #include <asm/arch/clk.h>
18 #if !defined(CONFIG_AT91FAMILY)
19 # error You need to define CONFIG_AT91FAMILY in your board config!
22 DECLARE_GLOBAL_DATA_PTR;
25 * We're using the SAMA5D3x PITC in 32 bit mode, by
26 * setting the 20 bit counter period to its maximum (0xfffff).
27 * (See the relevant data sheets to understand that this really works)
29 * We do also mimic the typical powerpc way of incrementing
30 * two 32 bit registers called tbl and tbu.
32 * Those registers increment at 1/16 the main clock rate.
35 #define TIMER_LOAD_VAL 0xfffff
38 * Use the PITC in full 32 bit incrementing mode
42 at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
44 /* Enable PITC Clock */
45 at91_periph_clk_enable(ATMEL_ID_PIT);
48 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
50 gd->arch.timer_rate_hz = get_pit_clk_rate() / 16;
56 * Return the number of timer ticks per second.
60 return gd->arch.timer_rate_hz;