2 * (C) Copyright 2014 DENX Software Engineering
3 * Heiko Schocher <hs@denx.de>
6 * Copyright (C) 2013 Atmel Corporation
7 * Bo Shen <voice.shen@atmel.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/at91_common.h>
15 #include <asm/arch/at91sam9_matrix.h>
16 #include <asm/arch/at91_pit.h>
17 #include <asm/arch/at91_pmc.h>
18 #include <asm/arch/at91_rstc.h>
19 #include <asm/arch/at91_wdt.h>
20 #include <asm/arch/clk.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 static void enable_ext_reset(void)
27 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
29 writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr);
32 void lowlevel_clock_init(void)
34 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
36 if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) {
37 /* Enable Main Oscillator */
38 writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor);
40 /* Wait until Main Oscillator is stable */
41 while (!(readl(&pmc->sr) & AT91_PMC_MOSCS))
45 /* After stabilization, switch to Main Oscillator */
46 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) {
49 tmp = readl(&pmc->mckr);
51 tmp |= AT91_PMC_CSS_MAIN;
52 writel(tmp, &pmc->mckr);
53 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
56 tmp &= ~AT91_PMC_PRES;
57 tmp |= AT91_PMC_PRES_1;
58 writel(tmp, &pmc->mckr);
59 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
66 void __weak matrix_init(void)
70 void __weak at91_spl_board_init(void)
74 void __weak spl_board_init(void)
78 void board_init_f(ulong dummy)
80 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
82 lowlevel_clock_init();
86 * At this stage the main oscillator is supposed to be enabled
89 writel(0x00, &pmc->pllicpr);
91 /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
92 at91_plla_init(CONFIG_SYS_AT91_PLLA);
94 /* PCK = PLLA = 2 * MCK */
95 at91_mck_init(CONFIG_SYS_MCKR);
97 /* Switch MCK on PLLA output */
98 at91_mck_init(CONFIG_SYS_MCKR_CSS);
100 #if defined(CONFIG_SYS_AT91_PLLB)
102 at91_pllb_init(CONFIG_SYS_AT91_PLLB);
105 /* Enable External Reset */
108 /* Initialize matrix */
111 gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
113 * init timer long enough for using in spl.
117 /* enable clocks for all PIOs */
118 #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
119 at91_periph_clk_enable(ATMEL_ID_PIOAB);
120 at91_periph_clk_enable(ATMEL_ID_PIOCD);
122 at91_periph_clk_enable(ATMEL_ID_PIOA);
123 at91_periph_clk_enable(ATMEL_ID_PIOB);
124 at91_periph_clk_enable(ATMEL_ID_PIOC);
127 #if defined(CONFIG_SPL_SERIAL_SUPPORT)
129 at91_seriald_hw_init();
130 preloader_console_init();
135 at91_spl_board_init();