2 * SoC-specific code for tms320dm644x chips
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
6 * Copyright (C) 2004 Texas Instruments.
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/hardware.h>
15 #define PINMUX0_EMACEN (1 << 31)
16 #define PINMUX0_AECS5 (1 << 11)
17 #define PINMUX0_AECS4 (1 << 10)
19 #define PINMUX1_I2C (1 << 7)
20 #define PINMUX1_UART1 (1 << 1)
21 #define PINMUX1_UART0 (1 << 0)
24 void davinci_enable_uart0(void)
26 lpsc_on(DAVINCI_LPSC_UART0);
28 /* Bringup UART0 out of reset */
29 REG(UART0_PWREMU_MGMT) = 0x00006001;
31 /* Enable UART0 MUX lines */
32 REG(PINMUX1) |= PINMUX1_UART0;
35 #ifdef CONFIG_DRIVER_TI_EMAC
36 void davinci_enable_emac(void)
38 lpsc_on(DAVINCI_LPSC_EMAC);
39 lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
40 lpsc_on(DAVINCI_LPSC_MDIO);
42 /* Enable GIO3.3V cells used for EMAC */
43 REG(VDD3P3V_PWDN) = 0;
46 REG(PINMUX0) |= PINMUX0_EMACEN;
50 #ifdef CONFIG_SYS_I2C_DAVINCI
51 void davinci_enable_i2c(void)
53 lpsc_on(DAVINCI_LPSC_I2C);
55 /* Enable I2C pin Mux */
56 REG(PINMUX1) |= PINMUX1_I2C;
60 void davinci_errata_workarounds(void)
63 * Workaround for TMS320DM6446 errata 1.3.22:
64 * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
65 * Revision(s) Affected: 1.3 and earlier
67 REG(PSC_SILVER_BULLET) = 0;
70 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
71 * as suggested in TMS320DM6446 errata 2.1.2:
73 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
74 * low priority modules can occupy the bus and prevent high priority
75 * modules like the VPSS from getting the required DDR2 throughput.
76 * A hex value of 0x20 should provide a good ARM (cache enabled)
77 * performance and still allow good utilization by the VPSS or other