git.sur5r.net Git - u-boot/blob - arch/arm/mach-davinci/timer.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2003
   4  * Texas Instruments <www.ti.com>
   5  *
   6  * (C) Copyright 2002
   7  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8  * Marius Groeger <mgroeger@sysgo.de>
   9  *
  10  * (C) Copyright 2002
  11  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  12  * Alex Zuepke <azu@sysgo.de>
  13  *
  14  * (C) Copyright 2002-2004
  15  * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  16  *
  17  * (C) Copyright 2004
  18  * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
  19  *
  20  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/timer_defs.h>
  26 #include <div64.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 static struct davinci_timer * const timer =
  31         (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
  32
  33 #define TIMER_LOAD_VAL  0xffffffff
  34
  35 #define TIM_CLK_DIV     16
  36
  37 int timer_init(void)
  38 {
  39         /* We are using timer34 in unchained 32-bit mode, full speed */
  40         writel(0x0, &timer->tcr);
  41         writel(0x0, &timer->tgcr);
  42         writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
  43         writel(0x0, &timer->tim34);
  44         writel(TIMER_LOAD_VAL, &timer->prd34);
  45         writel(2 << 22, &timer->tcr);
  46         gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
  47         gd->arch.timer_reset_value = 0;
  48
  49         return(0);
  50 }
  51
  52 /*
  53  * Get the current 64 bit timer tick count
  54  */
  55 unsigned long long get_ticks(void)
  56 {
  57         unsigned long now = readl(&timer->tim34);
  58
  59         /* increment tbu if tbl has rolled over */
  60         if (now < gd->arch.tbl)
  61                 gd->arch.tbu++;
  62         gd->arch.tbl = now;
  63
  64         return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
  65 }
  66
  67 ulong get_timer(ulong base)
  68 {
  69         unsigned long long timer_diff;
  70
  71         timer_diff = get_ticks() - gd->arch.timer_reset_value;
  72
  73         return lldiv(timer_diff,
  74                      (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
  75 }
  76
  77 void __udelay(unsigned long usec)
  78 {
  79         unsigned long long endtime;
  80
  81         endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
  82                         1000000UL);
  83         endtime += get_ticks();
  84
  85         while (get_ticks() < endtime)
  86                 ;
  87 }
  88
  89 /*
  90  * This function is derived from PowerPC code (timebase clock frequency).
  91  * On ARM it returns the number of timer ticks per second.
  92  */
  93 ulong get_tbclk(void)
  94 {
  95         return gd->arch.timer_rate_hz;
  96 }
  97
  98 #ifdef CONFIG_HW_WATCHDOG
  99 static struct davinci_timer * const wdttimer =
 100         (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
 101
 102 /*
 103  * See prufw2.pdf for using Timer as a WDT
 104  */
 105 void davinci_hw_watchdog_enable(void)
 106 {
 107         writel(0x0, &wdttimer->tcr);
 108         writel(0x0, &wdttimer->tgcr);
 109         /* TIMMODE = 2h */
 110         writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
 111         writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
 112         writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
 113         writel(2 << 22, &wdttimer->tcr);
 114         writel(0x0, &wdttimer->tim12);
 115         writel(0x0, &wdttimer->tim34);
 116         /* set WDEN bit, WDKEY 0xa5c6 */
 117         writel(0xa5c64000, &wdttimer->wdtcr);
 118         /* clear counter register */
 119         writel(0xda7e4000, &wdttimer->wdtcr);
 120 }
 121
 122 void davinci_hw_watchdog_reset(void)
 123 {
 124         writel(0xa5c64000, &wdttimer->wdtcr);
 125         writel(0xda7e4000, &wdttimer->wdtcr);
 126 }
 127 #endif