1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Samsung Electronics
4 * Minkyu Kang <mk7.kang@samsung.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/clk.h>
11 #include <asm/arch/periph.h>
13 #define PLL_DIV_1024 1024
14 #define PLL_DIV_65535 65535
15 #define PLL_DIV_65536 65536
17 * This structure is to store the src bit, div bit and prediv bit
18 * positions of the peripheral clocks of the src and div registers
30 static struct clk_bit_info exynos5_bit_info[] = {
31 /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
32 {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
33 {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
34 {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
35 {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
36 {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
37 {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
38 {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
39 {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
40 {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0},
41 {PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0},
42 {PERIPH_ID_I2C6, -1, 0x7, 0x7, -1, 24, 0},
43 {PERIPH_ID_I2C7, -1, 0x7, 0x7, -1, 24, 0},
44 {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 16, 0, 8},
45 {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 20, 16, 24},
46 {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 24, 0, 8},
47 {PERIPH_ID_SDMMC0, 0xf, 0xf, 0xff, 0, 0, 8},
48 {PERIPH_ID_SDMMC1, 0xf, 0xf, 0xff, 4, 16, 24},
49 {PERIPH_ID_SDMMC2, 0xf, 0xf, 0xff, 8, 0, 8},
50 {PERIPH_ID_SDMMC3, 0xf, 0xf, 0xff, 12, 16, 24},
51 {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
52 {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
53 {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 0, 0, 4},
54 {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 4, 12, 16},
55 {PERIPH_ID_SDMMC4, 0xf, 0xf, 0xff, 16, 0, 8},
56 {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 0, -1},
57 {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 0, -1},
58 {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 0, -1},
59 {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 0, -1},
60 {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 0, -1},
62 {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
65 static struct clk_bit_info exynos542x_bit_info[] = {
66 /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
67 {PERIPH_ID_UART0, 0xf, 0xf, -1, 4, 8, -1},
68 {PERIPH_ID_UART1, 0xf, 0xf, -1, 8, 12, -1},
69 {PERIPH_ID_UART2, 0xf, 0xf, -1, 12, 16, -1},
70 {PERIPH_ID_UART3, 0xf, 0xf, -1, 16, 20, -1},
71 {PERIPH_ID_I2C0, -1, 0x3f, -1, -1, 8, -1},
72 {PERIPH_ID_I2C1, -1, 0x3f, -1, -1, 8, -1},
73 {PERIPH_ID_I2C2, -1, 0x3f, -1, -1, 8, -1},
74 {PERIPH_ID_I2C3, -1, 0x3f, -1, -1, 8, -1},
75 {PERIPH_ID_I2C4, -1, 0x3f, -1, -1, 8, -1},
76 {PERIPH_ID_I2C5, -1, 0x3f, -1, -1, 8, -1},
77 {PERIPH_ID_I2C6, -1, 0x3f, -1, -1, 8, -1},
78 {PERIPH_ID_I2C7, -1, 0x3f, -1, -1, 8, -1},
79 {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 20, 20, 8},
80 {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 24, 24, 16},
81 {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 28, 28, 24},
82 {PERIPH_ID_SDMMC0, 0x7, 0x3ff, -1, 8, 0, -1},
83 {PERIPH_ID_SDMMC1, 0x7, 0x3ff, -1, 12, 10, -1},
84 {PERIPH_ID_SDMMC2, 0x7, 0x3ff, -1, 16, 20, -1},
85 {PERIPH_ID_I2C8, -1, 0x3f, -1, -1, 8, -1},
86 {PERIPH_ID_I2C9, -1, 0x3f, -1, -1, 8, -1},
87 {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
88 {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
89 {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 12, 16, 0},
90 {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 16, 20, 8},
91 {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 28, -1},
92 {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 28, -1},
93 {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 28, -1},
94 {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 28, -1},
95 {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 28, -1},
96 {PERIPH_ID_I2C10, -1, 0x3f, -1, -1, 8, -1},
98 {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
101 /* Epll Clock division values to achive different frequency output */
102 static struct set_epll_con_val exynos5_epll_div[] = {
103 { 192000000, 0, 48, 3, 1, 0 },
104 { 180000000, 0, 45, 3, 1, 0 },
105 { 73728000, 1, 73, 3, 3, 47710 },
106 { 67737600, 1, 90, 4, 3, 20762 },
107 { 49152000, 0, 49, 3, 3, 9961 },
108 { 45158400, 0, 45, 3, 3, 10381 },
109 { 180633600, 0, 45, 3, 1, 10381 }
112 /* exynos: return pll clock frequency */
113 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
115 unsigned long m, p, s = 0, mask, fout;
119 * APLL_CON: MIDV [25:16]
120 * MPLL_CON: MIDV [25:16]
121 * EPLL_CON: MIDV [24:16]
122 * VPLL_CON: MIDV [24:16]
123 * BPLL_CON: MIDV [25:16]: Exynos5
125 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
131 m = (r >> 16) & mask;
138 freq = CONFIG_SYS_CLK_FREQ;
140 if (pllreg == EPLL || pllreg == RPLL) {
142 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
143 fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
144 } else if (pllreg == VPLL) {
149 * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
152 * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
155 * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
157 if (proid_is_exynos4210())
159 else if (proid_is_exynos4412())
161 else if (proid_is_exynos5250() || proid_is_exynos5420() ||
162 proid_is_exynos5422())
167 fout = (m + k / div) * (freq / (p * (1 << s)));
170 * Exynos4412 / Exynos5250
171 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
174 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
176 if (proid_is_exynos4210())
177 fout = m * (freq / (p * (1 << (s - 1))));
179 fout = m * (freq / (p * (1 << s)));
184 /* exynos4: return pll clock frequency */
185 static unsigned long exynos4_get_pll_clk(int pllreg)
187 struct exynos4_clock *clk =
188 (struct exynos4_clock *)samsung_get_base_clock();
189 unsigned long r, k = 0;
193 r = readl(&clk->apll_con0);
196 r = readl(&clk->mpll_con0);
199 r = readl(&clk->epll_con0);
200 k = readl(&clk->epll_con1);
203 r = readl(&clk->vpll_con0);
204 k = readl(&clk->vpll_con1);
207 printf("Unsupported PLL (%d)\n", pllreg);
211 return exynos_get_pll_clk(pllreg, r, k);
214 /* exynos4x12: return pll clock frequency */
215 static unsigned long exynos4x12_get_pll_clk(int pllreg)
217 struct exynos4x12_clock *clk =
218 (struct exynos4x12_clock *)samsung_get_base_clock();
219 unsigned long r, k = 0;
223 r = readl(&clk->apll_con0);
226 r = readl(&clk->mpll_con0);
229 r = readl(&clk->epll_con0);
230 k = readl(&clk->epll_con1);
233 r = readl(&clk->vpll_con0);
234 k = readl(&clk->vpll_con1);
237 printf("Unsupported PLL (%d)\n", pllreg);
241 return exynos_get_pll_clk(pllreg, r, k);
244 /* exynos5: return pll clock frequency */
245 static unsigned long exynos5_get_pll_clk(int pllreg)
247 struct exynos5_clock *clk =
248 (struct exynos5_clock *)samsung_get_base_clock();
249 unsigned long r, k = 0, fout;
250 unsigned int pll_div2_sel, fout_sel;
254 r = readl(&clk->apll_con0);
257 r = readl(&clk->mpll_con0);
260 r = readl(&clk->epll_con0);
261 k = readl(&clk->epll_con1);
264 r = readl(&clk->vpll_con0);
265 k = readl(&clk->vpll_con1);
268 r = readl(&clk->bpll_con0);
271 printf("Unsupported PLL (%d)\n", pllreg);
275 fout = exynos_get_pll_clk(pllreg, r, k);
277 /* According to the user manual, in EVT1 MPLL and BPLL always gives
278 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
279 if (pllreg == MPLL || pllreg == BPLL) {
280 pll_div2_sel = readl(&clk->pll_div2_sel);
284 fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
285 & MPLL_FOUT_SEL_MASK;
288 fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
289 & BPLL_FOUT_SEL_MASK;
303 /* exynos542x: return pll clock frequency */
304 static unsigned long exynos542x_get_pll_clk(int pllreg)
306 struct exynos5420_clock *clk =
307 (struct exynos5420_clock *)samsung_get_base_clock();
308 unsigned long r, k = 0;
312 r = readl(&clk->apll_con0);
315 r = readl(&clk->mpll_con0);
318 r = readl(&clk->epll_con0);
319 k = readl(&clk->epll_con1);
322 r = readl(&clk->vpll_con0);
323 k = readl(&clk->vpll_con1);
326 r = readl(&clk->bpll_con0);
329 r = readl(&clk->rpll_con0);
330 k = readl(&clk->rpll_con1);
333 r = readl(&clk->spll_con0);
336 printf("Unsupported PLL (%d)\n", pllreg);
340 return exynos_get_pll_clk(pllreg, r, k);
343 static struct clk_bit_info *get_clk_bit_info(int peripheral)
346 struct clk_bit_info *info;
348 if (proid_is_exynos5420() || proid_is_exynos5422())
349 info = exynos542x_bit_info;
351 info = exynos5_bit_info;
353 for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
354 if (info[i].id == peripheral)
358 if (info[i].id == PERIPH_ID_NONE)
359 debug("ERROR: Peripheral ID %d not found\n", peripheral);
364 static unsigned long exynos5_get_periph_rate(int peripheral)
366 struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
367 unsigned long sclk = 0;
368 unsigned int src = 0, div = 0, sub_div = 0;
369 struct exynos5_clock *clk =
370 (struct exynos5_clock *)samsung_get_base_clock();
372 switch (peripheral) {
373 case PERIPH_ID_UART0:
374 case PERIPH_ID_UART1:
375 case PERIPH_ID_UART2:
376 case PERIPH_ID_UART3:
377 src = readl(&clk->src_peric0);
378 div = readl(&clk->div_peric0);
385 src = readl(&clk->src_peric0);
386 div = readl(&clk->div_peric3);
389 src = readl(&clk->src_mau);
390 div = sub_div = readl(&clk->div_mau);
393 src = readl(&clk->src_peric1);
394 div = sub_div = readl(&clk->div_peric1);
397 src = readl(&clk->src_peric1);
398 div = sub_div = readl(&clk->div_peric2);
402 src = readl(&clk->sclk_src_isp);
403 div = sub_div = readl(&clk->sclk_div_isp);
405 case PERIPH_ID_SDMMC0:
406 case PERIPH_ID_SDMMC1:
407 src = readl(&clk->src_fsys);
408 div = sub_div = readl(&clk->div_fsys1);
410 case PERIPH_ID_SDMMC2:
411 case PERIPH_ID_SDMMC3:
412 src = readl(&clk->src_fsys);
413 div = sub_div = readl(&clk->div_fsys2);
423 src = EXYNOS_SRC_MPLL;
424 div = readl(&clk->div_top1);
425 sub_div = readl(&clk->div_top0);
428 debug("%s: invalid peripheral %d", __func__, peripheral);
432 if (bit_info->src_bit >= 0)
433 src = (src >> bit_info->src_bit) & bit_info->src_mask;
436 case EXYNOS_SRC_MPLL:
437 sclk = exynos5_get_pll_clk(MPLL);
439 case EXYNOS_SRC_EPLL:
440 sclk = exynos5_get_pll_clk(EPLL);
442 case EXYNOS_SRC_VPLL:
443 sclk = exynos5_get_pll_clk(VPLL);
446 debug("%s: EXYNOS_SRC %d not supported\n", __func__, src);
450 /* Clock divider ratio for this peripheral */
451 if (bit_info->div_bit >= 0)
452 div = (div >> bit_info->div_bit) & bit_info->div_mask;
454 /* Clock pre-divider ratio for this peripheral */
455 if (bit_info->prediv_bit >= 0)
456 sub_div = (sub_div >> bit_info->prediv_bit)
457 & bit_info->prediv_mask;
459 /* Calculate and return required clock rate */
460 return (sclk / (div + 1)) / (sub_div + 1);
463 static unsigned long exynos542x_get_periph_rate(int peripheral)
465 struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
466 unsigned long sclk = 0;
467 unsigned int src = 0, div = 0, sub_div = 0;
468 struct exynos5420_clock *clk =
469 (struct exynos5420_clock *)samsung_get_base_clock();
471 switch (peripheral) {
472 case PERIPH_ID_UART0:
473 case PERIPH_ID_UART1:
474 case PERIPH_ID_UART2:
475 case PERIPH_ID_UART3:
481 src = readl(&clk->src_peric0);
482 div = readl(&clk->div_peric0);
487 src = readl(&clk->src_peric1);
488 div = readl(&clk->div_peric1);
489 sub_div = readl(&clk->div_peric4);
493 src = readl(&clk->src_isp);
494 div = readl(&clk->div_isp1);
495 sub_div = readl(&clk->div_isp1);
497 case PERIPH_ID_SDMMC0:
498 case PERIPH_ID_SDMMC1:
499 case PERIPH_ID_SDMMC2:
500 case PERIPH_ID_SDMMC3:
501 src = readl(&clk->src_fsys);
502 div = readl(&clk->div_fsys1);
514 case PERIPH_ID_I2C10:
515 src = EXYNOS542X_SRC_MPLL;
516 div = readl(&clk->div_top1);
519 debug("%s: invalid peripheral %d", __func__, peripheral);
523 if (bit_info->src_bit >= 0)
524 src = (src >> bit_info->src_bit) & bit_info->src_mask;
527 case EXYNOS542X_SRC_MPLL:
528 sclk = exynos542x_get_pll_clk(MPLL);
530 case EXYNOS542X_SRC_SPLL:
531 sclk = exynos542x_get_pll_clk(SPLL);
533 case EXYNOS542X_SRC_EPLL:
534 sclk = exynos542x_get_pll_clk(EPLL);
536 case EXYNOS542X_SRC_RPLL:
537 sclk = exynos542x_get_pll_clk(RPLL);
540 debug("%s: EXYNOS542X_SRC %d not supported", __func__, src);
544 /* Clock divider ratio for this peripheral */
545 if (bit_info->div_bit >= 0)
546 div = (div >> bit_info->div_bit) & bit_info->div_mask;
548 /* Clock pre-divider ratio for this peripheral */
549 if (bit_info->prediv_bit >= 0)
550 sub_div = (sub_div >> bit_info->prediv_bit)
551 & bit_info->prediv_mask;
553 /* Calculate and return required clock rate */
554 return (sclk / (div + 1)) / (sub_div + 1);
557 unsigned long clock_get_periph_rate(int peripheral)
559 if (cpu_is_exynos5()) {
560 if (proid_is_exynos5420() || proid_is_exynos5422())
561 return exynos542x_get_periph_rate(peripheral);
562 return exynos5_get_periph_rate(peripheral);
568 /* exynos4: return ARM clock frequency */
569 static unsigned long exynos4_get_arm_clk(void)
571 struct exynos4_clock *clk =
572 (struct exynos4_clock *)samsung_get_base_clock();
574 unsigned long armclk;
575 unsigned int core_ratio;
576 unsigned int core2_ratio;
578 div = readl(&clk->div_cpu0);
580 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
581 core_ratio = (div >> 0) & 0x7;
582 core2_ratio = (div >> 28) & 0x7;
584 armclk = get_pll_clk(APLL) / (core_ratio + 1);
585 armclk /= (core2_ratio + 1);
590 /* exynos4x12: return ARM clock frequency */
591 static unsigned long exynos4x12_get_arm_clk(void)
593 struct exynos4x12_clock *clk =
594 (struct exynos4x12_clock *)samsung_get_base_clock();
596 unsigned long armclk;
597 unsigned int core_ratio;
598 unsigned int core2_ratio;
600 div = readl(&clk->div_cpu0);
602 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
603 core_ratio = (div >> 0) & 0x7;
604 core2_ratio = (div >> 28) & 0x7;
606 armclk = get_pll_clk(APLL) / (core_ratio + 1);
607 armclk /= (core2_ratio + 1);
612 /* exynos5: return ARM clock frequency */
613 static unsigned long exynos5_get_arm_clk(void)
615 struct exynos5_clock *clk =
616 (struct exynos5_clock *)samsung_get_base_clock();
618 unsigned long armclk;
619 unsigned int arm_ratio;
620 unsigned int arm2_ratio;
622 div = readl(&clk->div_cpu0);
624 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
625 arm_ratio = (div >> 0) & 0x7;
626 arm2_ratio = (div >> 28) & 0x7;
628 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
629 armclk /= (arm2_ratio + 1);
634 /* exynos4: return pwm clock frequency */
635 static unsigned long exynos4_get_pwm_clk(void)
637 struct exynos4_clock *clk =
638 (struct exynos4_clock *)samsung_get_base_clock();
639 unsigned long pclk, sclk;
643 if (s5p_get_cpu_rev() == 0) {
648 sel = readl(&clk->src_peril0);
649 sel = (sel >> 24) & 0xf;
652 sclk = get_pll_clk(MPLL);
654 sclk = get_pll_clk(EPLL);
656 sclk = get_pll_clk(VPLL);
664 ratio = readl(&clk->div_peril3);
666 } else if (s5p_get_cpu_rev() == 1) {
667 sclk = get_pll_clk(MPLL);
672 pclk = sclk / (ratio + 1);
677 /* exynos4x12: return pwm clock frequency */
678 static unsigned long exynos4x12_get_pwm_clk(void)
680 unsigned long pclk, sclk;
683 sclk = get_pll_clk(MPLL);
686 pclk = sclk / (ratio + 1);
691 /* exynos4: return uart clock frequency */
692 static unsigned long exynos4_get_uart_clk(int dev_index)
694 struct exynos4_clock *clk =
695 (struct exynos4_clock *)samsung_get_base_clock();
696 unsigned long uclk, sclk;
709 sel = readl(&clk->src_peril0);
710 sel = (sel >> (dev_index << 2)) & 0xf;
713 sclk = get_pll_clk(MPLL);
715 sclk = get_pll_clk(EPLL);
717 sclk = get_pll_clk(VPLL);
726 * UART3_RATIO [12:15]
727 * UART4_RATIO [16:19]
728 * UART5_RATIO [23:20]
730 ratio = readl(&clk->div_peril0);
731 ratio = (ratio >> (dev_index << 2)) & 0xf;
733 uclk = sclk / (ratio + 1);
738 /* exynos4x12: return uart clock frequency */
739 static unsigned long exynos4x12_get_uart_clk(int dev_index)
741 struct exynos4x12_clock *clk =
742 (struct exynos4x12_clock *)samsung_get_base_clock();
743 unsigned long uclk, sclk;
755 sel = readl(&clk->src_peril0);
756 sel = (sel >> (dev_index << 2)) & 0xf;
759 sclk = get_pll_clk(MPLL);
761 sclk = get_pll_clk(EPLL);
763 sclk = get_pll_clk(VPLL);
772 * UART3_RATIO [12:15]
773 * UART4_RATIO [16:19]
775 ratio = readl(&clk->div_peril0);
776 ratio = (ratio >> (dev_index << 2)) & 0xf;
778 uclk = sclk / (ratio + 1);
783 static unsigned long exynos4_get_mmc_clk(int dev_index)
785 struct exynos4_clock *clk =
786 (struct exynos4_clock *)samsung_get_base_clock();
787 unsigned long uclk, sclk;
788 unsigned int sel, ratio, pre_ratio;
791 sel = readl(&clk->src_fsys);
792 sel = (sel >> (dev_index << 2)) & 0xf;
795 sclk = get_pll_clk(MPLL);
797 sclk = get_pll_clk(EPLL);
799 sclk = get_pll_clk(VPLL);
806 ratio = readl(&clk->div_fsys1);
807 pre_ratio = readl(&clk->div_fsys1);
811 ratio = readl(&clk->div_fsys2);
812 pre_ratio = readl(&clk->div_fsys2);
815 ratio = readl(&clk->div_fsys3);
816 pre_ratio = readl(&clk->div_fsys3);
822 if (dev_index == 1 || dev_index == 3)
825 ratio = (ratio >> shift) & 0xf;
826 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
827 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
832 /* exynos4: set the mmc clock */
833 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
835 struct exynos4_clock *clk =
836 (struct exynos4_clock *)samsung_get_base_clock();
837 unsigned int addr, clear_bit, set_bit;
841 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
843 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
848 addr = (unsigned int)&clk->div_fsys1;
849 clear_bit = MASK_PRE_RATIO(dev_index);
850 set_bit = SET_PRE_RATIO(dev_index, div);
851 } else if (dev_index == 4) {
852 addr = (unsigned int)&clk->div_fsys3;
854 /* MMC4 is controlled with the MMC4_RATIO value */
855 clear_bit = MASK_RATIO(dev_index);
856 set_bit = SET_RATIO(dev_index, div);
858 addr = (unsigned int)&clk->div_fsys2;
860 clear_bit = MASK_PRE_RATIO(dev_index);
861 set_bit = SET_PRE_RATIO(dev_index, div);
864 clrsetbits_le32(addr, clear_bit, set_bit);
867 /* exynos5: set the mmc clock */
868 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
870 struct exynos5_clock *clk =
871 (struct exynos5_clock *)samsung_get_base_clock();
876 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
878 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
881 addr = (unsigned int)&clk->div_fsys1;
883 addr = (unsigned int)&clk->div_fsys2;
887 clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
888 (div & 0xff) << ((dev_index << 4) + 8));
891 /* exynos5: set the mmc clock */
892 static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
894 struct exynos5420_clock *clk =
895 (struct exynos5420_clock *)samsung_get_base_clock();
905 addr = (unsigned int)&clk->div_fsys1;
906 shift = dev_index * 10;
908 clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
911 /* get_lcd_clk: return lcd clock frequency */
912 static unsigned long exynos4_get_lcd_clk(void)
914 struct exynos4_clock *clk =
915 (struct exynos4_clock *)samsung_get_base_clock();
916 unsigned long pclk, sclk;
924 sel = readl(&clk->src_lcd0);
933 sclk = get_pll_clk(MPLL);
935 sclk = get_pll_clk(EPLL);
937 sclk = get_pll_clk(VPLL);
945 ratio = readl(&clk->div_lcd0);
948 pclk = sclk / (ratio + 1);
953 /* get_lcd_clk: return lcd clock frequency */
954 static unsigned long exynos5_get_lcd_clk(void)
956 struct exynos5_clock *clk =
957 (struct exynos5_clock *)samsung_get_base_clock();
958 unsigned long pclk, sclk;
966 sel = readl(&clk->src_disp1_0);
975 sclk = get_pll_clk(MPLL);
977 sclk = get_pll_clk(EPLL);
979 sclk = get_pll_clk(VPLL);
987 ratio = readl(&clk->div_disp1_0);
990 pclk = sclk / (ratio + 1);
995 static unsigned long exynos5420_get_lcd_clk(void)
997 struct exynos5420_clock *clk =
998 (struct exynos5420_clock *)samsung_get_base_clock();
999 unsigned long pclk, sclk;
1009 sel = readl(&clk->src_disp10);
1013 sclk = get_pll_clk(SPLL);
1015 sclk = get_pll_clk(RPLL);
1021 ratio = readl(&clk->div_disp10);
1022 ratio = ratio & 0xf;
1024 pclk = sclk / (ratio + 1);
1029 static unsigned long exynos5800_get_lcd_clk(void)
1031 struct exynos5420_clock *clk =
1032 (struct exynos5420_clock *)samsung_get_base_clock();
1039 * CLKMUX_FIMD1 [6:4]
1041 sel = (readl(&clk->src_disp10) >> 4) & 0x7;
1045 * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
1046 * PLLs. The first element is a placeholder to bypass the
1049 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
1051 sclk = get_pll_clk(reg_map[sel]);
1053 sclk = CONFIG_SYS_CLK_FREQ;
1058 ratio = readl(&clk->div_disp10) & 0xf;
1060 return sclk / (ratio + 1);
1063 void exynos4_set_lcd_clk(void)
1065 struct exynos4_clock *clk =
1066 (struct exynos4_clock *)samsung_get_base_clock();
1078 setbits_le32(&clk->gate_block, 1 << 4);
1084 * MDNIE_PWM0_SEL [8:11]
1086 * set lcd0 src clock 0x6: SCLK_MPLL
1088 clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
1098 * Gating all clocks for FIMD0
1100 setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
1105 * MDNIE0_RATIO [7:4]
1106 * MDNIE_PWM0_RATIO [11:8]
1107 * MDNIE_PWM_PRE_RATIO [15:12]
1108 * MIPI0_RATIO [19:16]
1109 * MIPI0_PRE_RATIO [23:20]
1112 clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
1115 void exynos5_set_lcd_clk(void)
1117 struct exynos5_clock *clk =
1118 (struct exynos5_clock *)samsung_get_base_clock();
1130 setbits_le32(&clk->gate_block, 1 << 4);
1136 * MDNIE_PWM0_SEL [8:11]
1138 * set lcd0 src clock 0x6: SCLK_MPLL
1140 clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
1150 * Gating all clocks for FIMD0
1152 setbits_le32(&clk->gate_ip_disp1, 1 << 0);
1157 * MDNIE0_RATIO [7:4]
1158 * MDNIE_PWM0_RATIO [11:8]
1159 * MDNIE_PWM_PRE_RATIO [15:12]
1160 * MIPI0_RATIO [19:16]
1161 * MIPI0_PRE_RATIO [23:20]
1164 clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
1167 void exynos5420_set_lcd_clk(void)
1169 struct exynos5420_clock *clk =
1170 (struct exynos5420_clock *)samsung_get_base_clock();
1179 cfg = readl(&clk->src_disp10);
1182 writel(cfg, &clk->src_disp10);
1188 cfg = readl(&clk->div_disp10);
1191 writel(cfg, &clk->div_disp10);
1194 void exynos5800_set_lcd_clk(void)
1196 struct exynos5420_clock *clk =
1197 (struct exynos5420_clock *)samsung_get_base_clock();
1201 * Use RPLL for pixel clock
1202 * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
1203 * ==================
1206 cfg = readl(&clk->src_disp10) | (0x7 << 4);
1207 writel(cfg, &clk->src_disp10);
1213 clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);
1216 void exynos4_set_mipi_clk(void)
1218 struct exynos4_clock *clk =
1219 (struct exynos4_clock *)samsung_get_base_clock();
1225 * MDNIE_PWM0_SEL [8:11]
1227 * set mipi0 src clock 0x6: SCLK_MPLL
1229 clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
1235 * MDNIE_PWM0_MASK [8]
1237 * set src mask mipi0 0x1: Unmask
1239 setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
1249 * Gating all clocks for MIPI0
1251 setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
1256 * MDNIE0_RATIO [7:4]
1257 * MDNIE_PWM0_RATIO [11:8]
1258 * MDNIE_PWM_PRE_RATIO [15:12]
1259 * MIPI0_RATIO [19:16]
1260 * MIPI0_PRE_RATIO [23:20]
1263 clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
1266 int exynos5_set_epll_clk(unsigned long rate)
1268 unsigned int epll_con, epll_con_k;
1270 unsigned int lockcnt;
1272 struct exynos5_clock *clk =
1273 (struct exynos5_clock *)samsung_get_base_clock();
1275 epll_con = readl(&clk->epll_con0);
1276 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
1277 EPLL_CON0_LOCK_DET_EN_SHIFT) |
1278 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
1279 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
1280 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
1282 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
1283 if (exynos5_epll_div[i].freq_out == rate)
1287 if (i == ARRAY_SIZE(exynos5_epll_div))
1290 epll_con_k = exynos5_epll_div[i].k_dsm << 0;
1291 epll_con |= exynos5_epll_div[i].en_lock_det <<
1292 EPLL_CON0_LOCK_DET_EN_SHIFT;
1293 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
1294 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
1295 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
1298 * Required period ( in cycles) to genarate a stable clock output.
1299 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
1300 * frequency input (as per spec)
1302 lockcnt = 3000 * exynos5_epll_div[i].p_div;
1304 writel(lockcnt, &clk->epll_lock);
1305 writel(epll_con, &clk->epll_con0);
1306 writel(epll_con_k, &clk->epll_con1);
1308 start = get_timer(0);
1310 while (!(readl(&clk->epll_con0) &
1311 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
1312 if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
1313 debug("%s: Timeout waiting for EPLL lock\n", __func__);
1320 int exynos5_set_i2s_clk_source(unsigned int i2s_id)
1322 struct exynos5_clock *clk =
1323 (struct exynos5_clock *)samsung_get_base_clock();
1324 unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass();
1327 setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
1328 clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,
1329 (CLK_SRC_SCLK_EPLL));
1330 setbits_le32(audio_ass, AUDIO_CLKMUX_ASS);
1331 } else if (i2s_id == 1) {
1332 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
1333 (CLK_SRC_SCLK_EPLL));
1340 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
1341 unsigned int dst_frq,
1342 unsigned int i2s_id)
1344 struct exynos5_clock *clk =
1345 (struct exynos5_clock *)samsung_get_base_clock();
1348 if ((dst_frq == 0) || (src_frq == 0)) {
1349 debug("%s: Invalid requency input for prescaler\n", __func__);
1350 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1354 div = (src_frq / dst_frq);
1356 if (div > AUDIO_0_RATIO_MASK) {
1357 debug("%s: Frequency ratio is out of range\n",
1359 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1362 clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,
1363 (div & AUDIO_0_RATIO_MASK));
1364 } else if (i2s_id == 1) {
1365 if (div > AUDIO_1_RATIO_MASK) {
1366 debug("%s: Frequency ratio is out of range\n",
1368 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1371 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
1372 (div & AUDIO_1_RATIO_MASK));
1380 * Linearly searches for the most accurate main and fine stage clock scalars
1381 * (divisors) for a specified target frequency and scalar bit sizes by checking
1382 * all multiples of main_scalar_bits values. Will always return scalars up to or
1383 * slower than target.
1385 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
1386 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
1387 * @param input_freq Clock frequency to be scaled in Hz
1388 * @param target_freq Desired clock frequency in Hz
1389 * @param best_fine_scalar Pointer to store the fine stage divisor
1391 * @return best_main_scalar Main scalar for desired frequency or -1 if none
1394 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
1395 unsigned int fine_scalar_bits, unsigned int input_rate,
1396 unsigned int target_rate, unsigned int *best_fine_scalar)
1399 int best_main_scalar = -1;
1400 unsigned int best_error = target_rate;
1401 const unsigned int cap = (1 << fine_scalar_bits) - 1;
1402 const unsigned int loops = 1 << main_scaler_bits;
1404 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
1407 assert(best_fine_scalar != NULL);
1408 assert(main_scaler_bits <= fine_scalar_bits);
1410 *best_fine_scalar = 1;
1412 if (input_rate == 0 || target_rate == 0)
1415 if (target_rate >= input_rate)
1418 for (i = 1; i <= loops; i++) {
1419 const unsigned int effective_div =
1420 max(min(input_rate / i / target_rate, cap), 1U);
1421 const unsigned int effective_rate = input_rate / i /
1423 const int error = target_rate - effective_rate;
1425 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
1426 effective_rate, error);
1428 if (error >= 0 && error <= best_error) {
1430 best_main_scalar = i;
1431 *best_fine_scalar = effective_div;
1435 return best_main_scalar;
1438 static int exynos5_set_spi_clk(enum periph_id periph_id,
1441 struct exynos5_clock *clk =
1442 (struct exynos5_clock *)samsung_get_base_clock();
1445 unsigned shift, pre_shift;
1446 unsigned mask = 0xff;
1449 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1451 debug("%s: Cannot set clock rate for periph %d",
1452 __func__, periph_id);
1458 switch (periph_id) {
1459 case PERIPH_ID_SPI0:
1460 reg = &clk->div_peric1;
1464 case PERIPH_ID_SPI1:
1465 reg = &clk->div_peric1;
1469 case PERIPH_ID_SPI2:
1470 reg = &clk->div_peric2;
1474 case PERIPH_ID_SPI3:
1475 reg = &clk->sclk_div_isp;
1479 case PERIPH_ID_SPI4:
1480 reg = &clk->sclk_div_isp;
1485 debug("%s: Unsupported peripheral ID %d\n", __func__,
1489 clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
1490 clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
1495 static int exynos5420_set_spi_clk(enum periph_id periph_id,
1498 struct exynos5420_clock *clk =
1499 (struct exynos5420_clock *)samsung_get_base_clock();
1502 unsigned shift, pre_shift;
1503 unsigned div_mask = 0xf, pre_div_mask = 0xff;
1507 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1509 debug("%s: Cannot set clock rate for periph %d",
1510 __func__, periph_id);
1516 switch (periph_id) {
1517 case PERIPH_ID_SPI0:
1518 reg = &clk->div_peric1;
1520 pre_reg = &clk->div_peric4;
1523 case PERIPH_ID_SPI1:
1524 reg = &clk->div_peric1;
1526 pre_reg = &clk->div_peric4;
1529 case PERIPH_ID_SPI2:
1530 reg = &clk->div_peric1;
1532 pre_reg = &clk->div_peric4;
1535 case PERIPH_ID_SPI3:
1536 reg = &clk->div_isp1;
1538 pre_reg = &clk->div_isp1;
1541 case PERIPH_ID_SPI4:
1542 reg = &clk->div_isp1;
1544 pre_reg = &clk->div_isp1;
1548 debug("%s: Unsupported peripheral ID %d\n", __func__,
1553 clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
1554 clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
1555 (fine & pre_div_mask) << pre_shift);
1560 static unsigned long exynos4_get_i2c_clk(void)
1562 struct exynos4_clock *clk =
1563 (struct exynos4_clock *)samsung_get_base_clock();
1564 unsigned long sclk, aclk_100;
1567 sclk = get_pll_clk(APLL);
1569 ratio = (readl(&clk->div_top)) >> 4;
1571 aclk_100 = sclk / (ratio + 1);
1575 unsigned long get_pll_clk(int pllreg)
1577 if (cpu_is_exynos5()) {
1578 if (proid_is_exynos5420() || proid_is_exynos5422())
1579 return exynos542x_get_pll_clk(pllreg);
1580 return exynos5_get_pll_clk(pllreg);
1581 } else if (cpu_is_exynos4()) {
1582 if (proid_is_exynos4412())
1583 return exynos4x12_get_pll_clk(pllreg);
1584 return exynos4_get_pll_clk(pllreg);
1590 unsigned long get_arm_clk(void)
1592 if (cpu_is_exynos5()) {
1593 return exynos5_get_arm_clk();
1594 } else if (cpu_is_exynos4()) {
1595 if (proid_is_exynos4412())
1596 return exynos4x12_get_arm_clk();
1597 return exynos4_get_arm_clk();
1603 unsigned long get_i2c_clk(void)
1605 if (cpu_is_exynos5())
1606 return clock_get_periph_rate(PERIPH_ID_I2C0);
1607 else if (cpu_is_exynos4())
1608 return exynos4_get_i2c_clk();
1613 unsigned long get_pwm_clk(void)
1615 if (cpu_is_exynos5()) {
1616 return clock_get_periph_rate(PERIPH_ID_PWM0);
1617 } else if (cpu_is_exynos4()) {
1618 if (proid_is_exynos4412())
1619 return exynos4x12_get_pwm_clk();
1620 return exynos4_get_pwm_clk();
1626 unsigned long get_uart_clk(int dev_index)
1630 switch (dev_index) {
1632 id = PERIPH_ID_UART0;
1635 id = PERIPH_ID_UART1;
1638 id = PERIPH_ID_UART2;
1641 id = PERIPH_ID_UART3;
1644 debug("%s: invalid UART index %d", __func__, dev_index);
1648 if (cpu_is_exynos5()) {
1649 return clock_get_periph_rate(id);
1650 } else if (cpu_is_exynos4()) {
1651 if (proid_is_exynos4412())
1652 return exynos4x12_get_uart_clk(dev_index);
1653 return exynos4_get_uart_clk(dev_index);
1659 unsigned long get_mmc_clk(int dev_index)
1663 if (cpu_is_exynos4())
1664 return exynos4_get_mmc_clk(dev_index);
1666 switch (dev_index) {
1668 id = PERIPH_ID_SDMMC0;
1671 id = PERIPH_ID_SDMMC1;
1674 id = PERIPH_ID_SDMMC2;
1677 id = PERIPH_ID_SDMMC3;
1680 debug("%s: invalid MMC index %d", __func__, dev_index);
1684 return clock_get_periph_rate(id);
1687 void set_mmc_clk(int dev_index, unsigned int div)
1689 /* If want to set correct value, it needs to substract one from div.*/
1693 if (cpu_is_exynos5()) {
1694 if (proid_is_exynos5420() || proid_is_exynos5422())
1695 exynos5420_set_mmc_clk(dev_index, div);
1697 exynos5_set_mmc_clk(dev_index, div);
1698 } else if (cpu_is_exynos4()) {
1699 exynos4_set_mmc_clk(dev_index, div);
1703 unsigned long get_lcd_clk(void)
1705 if (cpu_is_exynos4()) {
1706 return exynos4_get_lcd_clk();
1707 } else if (cpu_is_exynos5()) {
1708 if (proid_is_exynos5420())
1709 return exynos5420_get_lcd_clk();
1710 else if (proid_is_exynos5422())
1711 return exynos5800_get_lcd_clk();
1713 return exynos5_get_lcd_clk();
1719 void set_lcd_clk(void)
1721 if (cpu_is_exynos4()) {
1722 exynos4_set_lcd_clk();
1723 } else if (cpu_is_exynos5()) {
1724 if (proid_is_exynos5250())
1725 exynos5_set_lcd_clk();
1726 else if (proid_is_exynos5420())
1727 exynos5420_set_lcd_clk();
1729 exynos5800_set_lcd_clk();
1733 void set_mipi_clk(void)
1735 if (cpu_is_exynos4())
1736 exynos4_set_mipi_clk();
1739 int set_spi_clk(int periph_id, unsigned int rate)
1741 if (cpu_is_exynos5()) {
1742 if (proid_is_exynos5420() || proid_is_exynos5422())
1743 return exynos5420_set_spi_clk(periph_id, rate);
1744 return exynos5_set_spi_clk(periph_id, rate);
1750 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
1751 unsigned int i2s_id)
1753 if (cpu_is_exynos5())
1754 return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id);
1759 int set_i2s_clk_source(unsigned int i2s_id)
1761 if (cpu_is_exynos5())
1762 return exynos5_set_i2s_clk_source(i2s_id);
1767 int set_epll_clk(unsigned long rate)
1769 if (cpu_is_exynos5())
1770 return exynos5_set_epll_clk(rate);