1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Samsung Electronics
5 * Author: Donghwa Lee <dh09.lee@samsung.com>
11 #define msleep(a) udelay(a * 1000)
13 #define DP_TIMEOUT_LOOP_COUNT 100
17 #define EXYNOS_DP_SUCCESS 0
24 struct edp_disp_info {
28 unsigned int h_sync_width;
29 unsigned int h_back_porch;
30 unsigned int h_front_porch;
33 unsigned int v_sync_width;
34 unsigned int v_back_porch;
35 unsigned int v_front_porch;
37 unsigned int v_sync_rate;
40 struct edp_link_train_info {
41 unsigned int lt_status;
44 unsigned int cr_loop[4];
48 struct edp_video_info {
49 unsigned int master_mode;
50 unsigned int bist_mode;
51 unsigned int bist_pattern;
53 unsigned int h_sync_polarity;
54 unsigned int v_sync_polarity;
55 unsigned int interlaced;
57 unsigned int color_space;
58 unsigned int dynamic_range;
59 unsigned int ycbcr_coeff;
60 unsigned int color_depth;
63 struct exynos_dp_priv {
64 struct edp_disp_info disp_info;
65 struct edp_link_train_info lt_info;
66 struct edp_video_info video_info;
68 /*below info get from panel during training*/
69 unsigned char lane_bw;
70 unsigned char lane_cnt;
71 unsigned char dpcd_rev;
72 /*support enhanced frame cap */
73 unsigned char dpcd_efc;
74 struct exynos_dp *regs;
77 enum analog_power_block {
116 DP_LANE_BW_1_62 = 0x06,
117 DP_LANE_BW_2_70 = 0x0a,
127 DP_DPCD_REV_10 = 0x10,
128 DP_DPCD_REV_11 = 0x11,
141 PRE_EMPHASIS_LEVEL_0,
142 PRE_EMPHASIS_LEVEL_1,
143 PRE_EMPHASIS_LEVEL_2,
144 PRE_EMPHASIS_LEVEL_3,
170 WHITE_GRAY_BALCKBAR_32,
171 WHITE_GRAY_BALCKBAR_64,
182 VIDEO_TIMING_FROM_CAPTURE,
183 VIDEO_TIMING_FROM_REGISTER
187 struct exynos_dp_platform_data {
188 struct exynos_dp_priv *edp_dev_info;
191 #ifdef CONFIG_EXYNOS_DP
192 unsigned int exynos_init_dp(void);
194 unsigned int exynos_init_dp(void)
200 #endif /* _DP_INFO_H */