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   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * SAMSUNG EXYNOS USB HOST EHCI Controller
   4  *
   5  * Copyright (C) 2012 Samsung Electronics Co.Ltd
   6  *      Vivek Gautam <gautam.vivek@samsung.com>
   7  */
   8
   9 #ifndef __ASM_ARM_ARCH_EHCI_H__
  10 #define __ASM_ARM_ARCH_EHCI_H__
  11
  12 #define CLK_24MHZ               5
  13
  14 #define PHYPWR_NORMAL_MASK_PHY0                 (0x39 << 0)
  15 #define PHYPWR_NORMAL_MASK_PHY1                 (0x7 << 6)
  16 #define PHYPWR_NORMAL_MASK_HSIC0                (0x7 << 9)
  17 #define PHYPWR_NORMAL_MASK_HSIC1                (0x7 << 12)
  18 #define RSTCON_HOSTPHY_SWRST                    (0xf << 3)
  19 #define RSTCON_SWRST                            (0x1 << 0)
  20
  21 #define HOST_CTRL0_PHYSWRSTALL                  (1 << 31)
  22 #define HOST_CTRL0_COMMONON_N                   (1 << 9)
  23 #define HOST_CTRL0_SIDDQ                        (1 << 6)
  24 #define HOST_CTRL0_FORCESLEEP                   (1 << 5)
  25 #define HOST_CTRL0_FORCESUSPEND                 (1 << 4)
  26 #define HOST_CTRL0_WORDINTERFACE                (1 << 3)
  27 #define HOST_CTRL0_UTMISWRST                    (1 << 2)
  28 #define HOST_CTRL0_LINKSWRST                    (1 << 1)
  29 #define HOST_CTRL0_PHYSWRST                     (1 << 0)
  30
  31 #define HOST_CTRL0_FSEL_MASK                    (7 << 16)
  32
  33 #define EHCICTRL_ENAINCRXALIGN                  (1 << 29)
  34 #define EHCICTRL_ENAINCR4                       (1 << 28)
  35 #define EHCICTRL_ENAINCR8                       (1 << 27)
  36 #define EHCICTRL_ENAINCR16                      (1 << 26)
  37
  38 #define HSIC_CTRL_REFCLKSEL                     (0x2)
  39 #define HSIC_CTRL_REFCLKSEL_MASK                (0x3)
  40 #define HSIC_CTRL_REFCLKSEL_SHIFT               (23)
  41
  42 #define HSIC_CTRL_REFCLKDIV_12                  (0x24)
  43 #define HSIC_CTRL_REFCLKDIV_MASK                (0x7f)
  44 #define HSIC_CTRL_REFCLKDIV_SHIFT               (16)
  45
  46 #define HSIC_CTRL_SIDDQ                         (0x1 << 6)
  47 #define HSIC_CTRL_FORCESLEEP                    (0x1 << 5)
  48 #define HSIC_CTRL_FORCESUSPEND                  (0x1 << 4)
  49 #define HSIC_CTRL_UTMISWRST                     (0x1 << 2)
  50 #define HSIC_CTRL_PHYSWRST                      (0x1 << 0)
  51
  52 /* Register map for PHY control */
  53 struct exynos_usb_phy {
  54         unsigned int usbphyctrl0;
  55         unsigned int usbphytune0;
  56         unsigned int reserved1[2];
  57         unsigned int hsicphyctrl1;
  58         unsigned int hsicphytune1;
  59         unsigned int reserved2[2];
  60         unsigned int hsicphyctrl2;
  61         unsigned int hsicphytune2;
  62         unsigned int reserved3[2];
  63         unsigned int ehcictrl;
  64         unsigned int ohcictrl;
  65         unsigned int usbotgsys;
  66         unsigned int reserved4;
  67         unsigned int usbotgtune;
  68 };
  69
  70 struct exynos4412_usb_phy {
  71         unsigned int usbphyctrl;
  72         unsigned int usbphyclk;
  73         unsigned int usbphyrstcon;
  74 };
  75
  76 /* Switch on the VBUS power. */
  77 int board_usb_vbus_init(void);
  78
  79 #endif /* __ASM_ARM_ARCH_EHCI_H__ */