2 * Copyright (C) 2012 Samsung Electronics
3 * Donghwa Lee <dh09.lee@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/power.h>
12 static void exynos4_mipi_phy_control(unsigned int dev_index,
15 struct exynos4_power *pmu =
16 (struct exynos4_power *)samsung_get_base_power();
17 unsigned int addr, cfg = 0;
20 addr = (unsigned int)&pmu->mipi_phy0_control;
22 addr = (unsigned int)&pmu->mipi_phy1_control;
27 cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
29 cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
34 void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
37 exynos4_mipi_phy_control(dev_index, enable);
40 void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
42 struct exynos5_power *power =
43 (struct exynos5_power *)samsung_get_base_power();
46 /* Enabling USBHOST_PHY */
47 setbits_le32(&power->usbhost_phy_control,
48 POWER_USB_HOST_PHY_CTRL_EN);
50 /* Disabling USBHOST_PHY */
51 clrbits_le32(&power->usbhost_phy_control,
52 POWER_USB_HOST_PHY_CTRL_EN);
56 void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
58 struct exynos4412_power *power =
59 (struct exynos4412_power *)samsung_get_base_power();
62 /* Enabling USBHOST_PHY */
63 setbits_le32(&power->usbhost_phy_control,
64 POWER_USB_HOST_PHY_CTRL_EN);
65 setbits_le32(&power->hsic1_phy_control,
66 POWER_USB_HOST_PHY_CTRL_EN);
67 setbits_le32(&power->hsic2_phy_control,
68 POWER_USB_HOST_PHY_CTRL_EN);
70 /* Disabling USBHOST_PHY */
71 clrbits_le32(&power->usbhost_phy_control,
72 POWER_USB_HOST_PHY_CTRL_EN);
73 clrbits_le32(&power->hsic1_phy_control,
74 POWER_USB_HOST_PHY_CTRL_EN);
75 clrbits_le32(&power->hsic2_phy_control,
76 POWER_USB_HOST_PHY_CTRL_EN);
80 void set_usbhost_phy_ctrl(unsigned int enable)
83 exynos5_set_usbhost_phy_ctrl(enable);
84 else if (cpu_is_exynos4())
85 if (proid_is_exynos4412())
86 exynos4412_set_usbhost_phy_ctrl(enable);
89 static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
91 struct exynos5_power *power =
92 (struct exynos5_power *)samsung_get_base_power();
95 /* Enabling USBDRD_PHY */
96 setbits_le32(&power->usbdrd_phy_control,
97 POWER_USB_DRD_PHY_CTRL_EN);
99 /* Disabling USBDRD_PHY */
100 clrbits_le32(&power->usbdrd_phy_control,
101 POWER_USB_DRD_PHY_CTRL_EN);
105 static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
107 struct exynos5420_power *power =
108 (struct exynos5420_power *)samsung_get_base_power();
111 /* Enabling USBDEV_PHY */
112 setbits_le32(&power->usbdev_phy_control,
113 POWER_USB_DRD_PHY_CTRL_EN);
114 setbits_le32(&power->usbdev1_phy_control,
115 POWER_USB_DRD_PHY_CTRL_EN);
117 /* Disabling USBDEV_PHY */
118 clrbits_le32(&power->usbdev_phy_control,
119 POWER_USB_DRD_PHY_CTRL_EN);
120 clrbits_le32(&power->usbdev1_phy_control,
121 POWER_USB_DRD_PHY_CTRL_EN);
125 void set_usbdrd_phy_ctrl(unsigned int enable)
127 if (cpu_is_exynos5()) {
128 if (proid_is_exynos5420() || proid_is_exynos5800())
129 exynos5420_set_usbdev_phy_ctrl(enable);
131 exynos5_set_usbdrd_phy_ctrl(enable);
135 static void exynos5_dp_phy_control(unsigned int enable)
138 struct exynos5_power *power =
139 (struct exynos5_power *)samsung_get_base_power();
141 cfg = readl(&power->dptx_phy_control);
143 cfg |= EXYNOS_DP_PHY_ENABLE;
145 cfg &= ~EXYNOS_DP_PHY_ENABLE;
147 writel(cfg, &power->dptx_phy_control);
150 void set_dp_phy_ctrl(unsigned int enable)
152 if (cpu_is_exynos5())
153 exynos5_dp_phy_control(enable);
156 static void exynos5_set_ps_hold_ctrl(void)
158 struct exynos5_power *power =
159 (struct exynos5_power *)samsung_get_base_power();
161 /* Set PS-Hold high */
162 setbits_le32(&power->ps_hold_control,
163 EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
167 * Set ps_hold data driving value high
168 * This enables the machine to stay powered on
169 * after the initial power-on condition goes away
170 * (e.g. power button).
172 void set_ps_hold_ctrl(void)
174 if (cpu_is_exynos5())
175 exynos5_set_ps_hold_ctrl();
179 static void exynos5_set_xclkout(void)
181 struct exynos5_power *power =
182 (struct exynos5_power *)samsung_get_base_power();
184 /* use xxti for xclk out */
185 clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
189 void set_xclkout(void)
191 if (cpu_is_exynos5())
192 exynos5_set_xclkout();
195 /* Enables hardware tripping to power off the system when TMU fails */
196 void set_hw_thermal_trip(void)
198 if (cpu_is_exynos5()) {
199 struct exynos5_power *power =
200 (struct exynos5_power *)samsung_get_base_power();
202 /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
203 setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
207 static uint32_t exynos5_get_reset_status(void)
209 struct exynos5_power *power =
210 (struct exynos5_power *)samsung_get_base_power();
212 return power->inform1;
215 static uint32_t exynos4_get_reset_status(void)
217 struct exynos4_power *power =
218 (struct exynos4_power *)samsung_get_base_power();
220 return power->inform1;
223 uint32_t get_reset_status(void)
225 if (cpu_is_exynos5())
226 return exynos5_get_reset_status();
228 return exynos4_get_reset_status();
231 static void exynos5_power_exit_wakeup(void)
233 struct exynos5_power *power =
234 (struct exynos5_power *)samsung_get_base_power();
235 typedef void (*resume_func)(void);
237 ((resume_func)power->inform0)();
240 static void exynos4_power_exit_wakeup(void)
242 struct exynos4_power *power =
243 (struct exynos4_power *)samsung_get_base_power();
244 typedef void (*resume_func)(void);
246 ((resume_func)power->inform0)();
249 void power_exit_wakeup(void)
251 if (cpu_is_exynos5())
252 exynos5_power_exit_wakeup();
254 exynos4_power_exit_wakeup();
257 unsigned int get_boot_mode(void)
259 unsigned int om_pin = samsung_get_base_power();
261 return readl(om_pin) & OM_PIN_MASK;