git.sur5r.net Git - u-boot/blob - arch/arm/mach-imx/ddrmc-vf610.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Toradex, Inc.
   4  *
   5  * Based on vf610twr:
   6  * Copyright 2013 Freescale Semiconductor, Inc.
   7  */
   8
   9 #include <asm/io.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux-vf610.h>
  12 #include <asm/arch/ddrmc-vf610.h>
  13
  14 void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
  15 {
  16         static const iomux_v3_cfg_t default_pads[] = {
  17                 VF610_PAD_DDR_A15__DDR_A_15,
  18                 VF610_PAD_DDR_A14__DDR_A_14,
  19                 VF610_PAD_DDR_A13__DDR_A_13,
  20                 VF610_PAD_DDR_A12__DDR_A_12,
  21                 VF610_PAD_DDR_A11__DDR_A_11,
  22                 VF610_PAD_DDR_A10__DDR_A_10,
  23                 VF610_PAD_DDR_A9__DDR_A_9,
  24                 VF610_PAD_DDR_A8__DDR_A_8,
  25                 VF610_PAD_DDR_A7__DDR_A_7,
  26                 VF610_PAD_DDR_A6__DDR_A_6,
  27                 VF610_PAD_DDR_A5__DDR_A_5,
  28                 VF610_PAD_DDR_A4__DDR_A_4,
  29                 VF610_PAD_DDR_A3__DDR_A_3,
  30                 VF610_PAD_DDR_A2__DDR_A_2,
  31                 VF610_PAD_DDR_A1__DDR_A_1,
  32                 VF610_PAD_DDR_A0__DDR_A_0,
  33                 VF610_PAD_DDR_BA2__DDR_BA_2,
  34                 VF610_PAD_DDR_BA1__DDR_BA_1,
  35                 VF610_PAD_DDR_BA0__DDR_BA_0,
  36                 VF610_PAD_DDR_CAS__DDR_CAS_B,
  37                 VF610_PAD_DDR_CKE__DDR_CKE_0,
  38                 VF610_PAD_DDR_CLK__DDR_CLK_0,
  39                 VF610_PAD_DDR_CS__DDR_CS_B_0,
  40                 VF610_PAD_DDR_D15__DDR_D_15,
  41                 VF610_PAD_DDR_D14__DDR_D_14,
  42                 VF610_PAD_DDR_D13__DDR_D_13,
  43                 VF610_PAD_DDR_D12__DDR_D_12,
  44                 VF610_PAD_DDR_D11__DDR_D_11,
  45                 VF610_PAD_DDR_D10__DDR_D_10,
  46                 VF610_PAD_DDR_D9__DDR_D_9,
  47                 VF610_PAD_DDR_D8__DDR_D_8,
  48                 VF610_PAD_DDR_D7__DDR_D_7,
  49                 VF610_PAD_DDR_D6__DDR_D_6,
  50                 VF610_PAD_DDR_D5__DDR_D_5,
  51                 VF610_PAD_DDR_D4__DDR_D_4,
  52                 VF610_PAD_DDR_D3__DDR_D_3,
  53                 VF610_PAD_DDR_D2__DDR_D_2,
  54                 VF610_PAD_DDR_D1__DDR_D_1,
  55                 VF610_PAD_DDR_D0__DDR_D_0,
  56                 VF610_PAD_DDR_DQM1__DDR_DQM_1,
  57                 VF610_PAD_DDR_DQM0__DDR_DQM_0,
  58                 VF610_PAD_DDR_DQS1__DDR_DQS_1,
  59                 VF610_PAD_DDR_DQS0__DDR_DQS_0,
  60                 VF610_PAD_DDR_RAS__DDR_RAS_B,
  61                 VF610_PAD_DDR_WE__DDR_WE_B,
  62                 VF610_PAD_DDR_ODT1__DDR_ODT_0,
  63                 VF610_PAD_DDR_ODT0__DDR_ODT_1,
  64                 VF610_PAD_DDR_RESETB,
  65         };
  66
  67         if ((pads == NULL) || (pads_count == 0)) {
  68                 pads = default_pads;
  69                 pads_count = ARRAY_SIZE(default_pads);
  70         }
  71
  72         imx_iomux_v3_setup_multiple_pads(pads, pads_count);
  73 }
  74
  75 static struct ddrmc_phy_setting default_phy_settings[] = {
  76         { DDRMC_PHY_DQ_TIMING,  0 },
  77         { DDRMC_PHY_DQ_TIMING, 16 },
  78         { DDRMC_PHY_DQ_TIMING, 32 },
  79
  80         { DDRMC_PHY_DQS_TIMING,  1 },
  81         { DDRMC_PHY_DQS_TIMING, 17 },
  82
  83         { DDRMC_PHY_CTRL,  2 },
  84         { DDRMC_PHY_CTRL, 18 },
  85         { DDRMC_PHY_CTRL, 34 },
  86
  87         { DDRMC_PHY_MASTER_CTRL,  3 },
  88         { DDRMC_PHY_MASTER_CTRL, 19 },
  89         { DDRMC_PHY_MASTER_CTRL, 35 },
  90
  91         { DDRMC_PHY_SLAVE_CTRL,  4 },
  92         { DDRMC_PHY_SLAVE_CTRL, 20 },
  93         { DDRMC_PHY_SLAVE_CTRL, 36 },
  94
  95         /* LPDDR2 only parameter */
  96         { DDRMC_PHY_OFF, 49 },
  97
  98         { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
  99
 100         /* Processor Pad ODT settings */
 101         { DDRMC_PHY_PROC_PAD_ODT, 52 },
 102
 103         /* end marker */
 104         { 0, -1 }
 105 };
 106
 107 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 108                           struct ddrmc_cr_setting *board_cr_settings,
 109                           struct ddrmc_phy_setting *board_phy_settings,
 110                           int col_diff, int row_diff)
 111 {
 112         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
 113         struct ddrmc_cr_setting *cr_setting;
 114         struct ddrmc_phy_setting *phy_setting;
 115
 116         writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
 117         writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
 118         writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);
 119
 120         writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
 121         writel(DDRMC_CR12_WRLAT(timings->wrlat) |
 122                    DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
 123         writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
 124                    DDRMC_CR13_TCCD(timings->tccd) |
 125                    DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
 126                    &ddrmr->cr[13]);
 127         writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
 128                    DDRMC_CR14_TWTR(timings->twtr) |
 129                    DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
 130         writel(DDRMC_CR16_TMRD(timings->tmrd) |
 131                    DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]);
 132         writel(DDRMC_CR17_TRAS_MAX(timings->tras_max) |
 133                    DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]);
 134         writel(DDRMC_CR18_TCKESR(timings->tckesr) |
 135                    DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
 136
 137         writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
 138         writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
 139                    DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
 140                    &ddrmr->cr[21]);
 141
 142         writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
 143         writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
 144                    DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
 145         writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
 146
 147         writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
 148         writel(DDRMC_CR26_TREF(timings->tref) |
 149                    DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
 150         writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
 151         writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
 152
 153         writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
 154         writel(DDRMC_CR31_TXSNR(timings->txsnr) |
 155                    DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]);
 156         writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
 157         writel(DDRMC_CR34_CKSRX(timings->cksrx) |
 158                    DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
 159
 160         writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
 161         writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
 162                    DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
 163
 164         writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
 165         writel(DDRMC_CR48_MR1_DA_0(70) |
 166                    DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]);
 167
 168         writel(DDRMC_CR66_ZQCL(timings->zqcl) |
 169                    DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]);
 170         writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]);
 171         writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
 172
 173         writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
 174         writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
 175
 176         writel(DDRMC_CR73_APREBIT(timings->aprebit) |
 177                    DDRMC_CR73_COL_DIFF(col_diff) |
 178                    DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
 179         writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
 180                    DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
 181                    DDRMC_CR74_AGE_CNT(timings->age_cnt),
 182                    &ddrmr->cr[74]);
 183         writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
 184                    DDRMC_CR75_PLEN, &ddrmr->cr[75]);
 185         writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
 186                    DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
 187         writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
 188                    DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
 189         writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
 190                    DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
 191         writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
 192
 193         writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
 194
 195         writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
 196                    DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
 197                    &ddrmr->cr[87]);
 198         writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
 199         writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
 200
 201         writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
 202         writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
 203                    DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
 204
 205         /* execute custom CR setting sequence (may be NULL) */
 206         cr_setting = board_cr_settings;
 207         if (cr_setting != NULL)
 208                 while (cr_setting->cr_rnum >= 0) {
 209                         writel(cr_setting->setting,
 210                                &ddrmr->cr[cr_setting->cr_rnum]);
 211                         cr_setting++;
 212                 }
 213
 214         /* perform default PHY settings (may be overridden by custom settings */
 215         phy_setting = default_phy_settings;
 216         while (phy_setting->phy_rnum >= 0) {
 217                 writel(phy_setting->setting,
 218                        &ddrmr->phy[phy_setting->phy_rnum]);
 219                 phy_setting++;
 220         }
 221
 222         /* execute custom PHY setting sequence (may be NULL) */
 223         phy_setting = board_phy_settings;
 224         if (phy_setting != NULL)
 225                 while (phy_setting->phy_rnum >= 0) {
 226                         writel(phy_setting->setting,
 227                                &ddrmr->phy[phy_setting->phy_rnum]);
 228                         phy_setting++;
 229                 }
 230
 231         /* all inits done, start the DDR controller */
 232         writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
 233
 234         while (!(readl(&ddrmr->cr[80]) && 0x100))
 235                 udelay(10);
 236 }