3 #include <asm/secure.h>
4 #include <asm/arch/imx-regs.h>
8 #define GPC_CPU_PGC_SW_PDN_REQ 0xfc
9 #define GPC_CPU_PGC_SW_PUP_REQ 0xf0
10 #define GPC_PGC_C1 0x840
12 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
14 /* below is for i.MX7D */
15 #define SRC_GPR1_MX7D 0x074
16 #define SRC_A7RCR0 0x004
17 #define SRC_A7RCR1 0x008
19 #define BP_SRC_A7RCR0_A7_CORE_RESET0 0
20 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
22 static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
24 writel(enable, GPC_IPS_BASE_ADDR + offset);
27 __secure void imx_gpcv2_set_core1_power(bool pdn)
29 u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
32 imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
34 val = readl(GPC_IPS_BASE_ADDR + reg);
35 val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
36 writel(val, GPC_IPS_BASE_ADDR + reg);
38 while ((readl(GPC_IPS_BASE_ADDR + reg) &
39 BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0)
42 imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
45 __secure void imx_enable_cpu_ca7(int cpu, bool enable)
49 mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
50 val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
51 val = enable ? val | mask : val & ~mask;
52 writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
55 __secure int imx_cpu_on(int fn, int cpu, int pc)
57 writel(pc, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
58 imx_gpcv2_set_core1_power(true);
59 imx_enable_cpu_ca7(cpu, true);
63 __secure int imx_cpu_off(int cpu)
65 imx_enable_cpu_ca7(cpu, false);
66 imx_gpcv2_set_core1_power(false);
67 writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);