2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/secure.h>
11 #include <asm/arch/imx-regs.h>
15 #define GPC_CPU_PGC_SW_PDN_REQ 0xfc
16 #define GPC_CPU_PGC_SW_PUP_REQ 0xf0
17 #define GPC_PGC_C1 0x840
19 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
21 /* below is for i.MX7D */
22 #define SRC_GPR1_MX7D 0x074
23 #define SRC_A7RCR0 0x004
24 #define SRC_A7RCR1 0x008
26 #define BP_SRC_A7RCR0_A7_CORE_RESET0 0
27 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
29 static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
31 writel(enable, GPC_IPS_BASE_ADDR + offset);
34 __secure void imx_gpcv2_set_core1_power(bool pdn)
36 u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
39 imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
41 val = readl(GPC_IPS_BASE_ADDR + reg);
42 val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
43 writel(val, GPC_IPS_BASE_ADDR + reg);
45 while ((readl(GPC_IPS_BASE_ADDR + reg) &
46 BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0)
49 imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
52 __secure void imx_enable_cpu_ca7(int cpu, bool enable)
56 mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
57 val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
58 val = enable ? val | mask : val & ~mask;
59 writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
62 __secure int imx_cpu_on(int fn, int cpu, int pc)
64 writel(pc, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
65 imx_gpcv2_set_core1_power(true);
66 imx_enable_cpu_ca7(cpu, true);
70 __secure int imx_cpu_off(int cpu)
72 imx_enable_cpu_ca7(cpu, false);
73 imx_gpcv2_set_core1_power(false);
74 writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);