2 * Keystone2: pll initialization
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/clock_defs.h>
14 /* DEV and ARM speed definitions as specified in DEVSPEED register */
15 int __weak speeds[DEVSPEED_NUMSPDS] = {
28 const struct keystone_pll_regs keystone_pll_regs[] = {
29 [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
30 [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
31 [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
32 [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
33 [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
36 static void wait_for_completion(const struct pll_init_data *data)
39 for (i = 0; i < 100; i++) {
41 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK))
46 static inline void bypass_main_pll(const struct pll_init_data *data)
48 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK |
51 /* 4 cycles of reference clock CLKIN*/
55 static void configure_mult_div(const struct pll_init_data *data)
57 u32 pllm, plld, bwadj;
59 pllm = data->pll_m - 1;
60 plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;
62 /* Program Multiplier */
63 if (data->pll == MAIN_PLL)
64 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
66 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
67 CFG_PLLCTL0_PLLM_MASK,
68 pllm << CFG_PLLCTL0_PLLM_SHIFT);
71 bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */
72 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
73 CFG_PLLCTL0_BWADJ_MASK,
74 (bwadj << CFG_PLLCTL0_BWADJ_SHIFT) &
75 CFG_PLLCTL0_BWADJ_MASK);
76 bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS;
77 clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
78 CFG_PLLCTL1_BWADJ_MASK, bwadj);
81 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
82 CFG_PLLCTL0_PLLD_MASK, plld);
85 void configure_main_pll(const struct pll_init_data *data)
87 u32 tmp, pllod, i, alnctl_val = 0;
90 pllod = data->pll_od - 1;
92 /* 100 micro sec for stabilization */
95 tmp = pllctl_reg_read(data->pll, secctl);
97 /* Check for Bypass */
98 if (tmp & SECCTL_BYPASS_MASK) {
99 setbits_le32(keystone_pll_regs[data->pll].reg1,
100 CFG_PLLCTL1_ENSAT_MASK);
102 bypass_main_pll(data);
104 /* Powerdown and powerup Main Pll */
105 pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK);
106 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
110 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
112 bypass_main_pll(data);
115 configure_mult_div(data);
117 /* Program Output Divider */
118 pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK,
119 ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK));
121 /* Program PLLDIVn */
122 wait_for_completion(data);
123 for (i = 0; i < PLLDIV_MAX; i++) {
125 offset = pllctl_reg(data->pll, div1) + i;
127 offset = pllctl_reg(data->pll, div4) + (i - 3);
129 if (divn_val[i] != -1) {
130 __raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset);
131 alnctl_val |= BIT(i);
136 pllctl_reg_setbits(data->pll, alnctl, alnctl_val);
138 * Set GOSET bit in PLLCMD to initiate the GO operation
139 * to change the divide
141 pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK);
142 wait_for_completion(data);
146 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
147 sdelay(21000); /* Wait for a minimum of 7 us*/
148 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
149 sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
152 pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK);
153 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK);
156 void configure_secondary_pll(const struct pll_init_data *data)
158 int pllod = data->pll_od - 1;
160 /* Enable Bypass mode */
161 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
162 setbits_le32(keystone_pll_regs[data->pll].reg0,
163 CFG_PLLCTL0_BYPASS_MASK);
165 /* Enable Glitch free bypass for ARM PLL */
166 if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
167 clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
169 configure_mult_div(data);
171 /* Program Output Divider */
172 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
173 CFG_PLLCTL0_CLKOD_MASK,
174 (pllod << CFG_PLLCTL0_CLKOD_SHIFT) &
175 CFG_PLLCTL0_CLKOD_MASK);
178 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
179 /* Wait for 5 micro seconds */
182 /* Select the Output of PASS PLL as input to PASS */
183 if (data->pll == PASS_PLL)
184 setbits_le32(keystone_pll_regs[data->pll].reg1,
185 CFG_PLLCTL1_PAPLL_MASK);
187 /* Select the Output of ARM PLL as input to ARM */
188 if (data->pll == TETRIS_PLL)
189 setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
191 clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
192 /* Wait for 500 * REFCLK cucles * (PLLD + 1) */
195 /* Switch to PLL mode */
196 clrbits_le32(keystone_pll_regs[data->pll].reg0,
197 CFG_PLLCTL0_BYPASS_MASK);
200 void init_pll(const struct pll_init_data *data)
202 if (data->pll == MAIN_PLL)
203 configure_main_pll(data);
205 configure_secondary_pll(data);
208 * This is required to provide a delay between multiple
209 * consequent PPL configurations
216 struct pll_init_data *data;
219 for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {
220 data = get_pll_init_data(pll);
226 static int get_max_speed(u32 val, u32 speed_supported)
230 /* Left most setbit gives the speed */
231 for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {
232 if ((val & BIT(speed)) & speed_supported)
233 return speeds[speed];
236 /* If no bit is set, use SPD800 */
240 static inline u32 read_efuse_bootrom(void)
242 if (cpu_is_k2hk() && (cpu_revision() <= 1))
243 return __raw_readl(KS2_REV1_DEVSPEED);
245 return __raw_readl(KS2_EFUSE_BOOTROM);
248 int get_max_arm_speed(void)
250 u32 armspeed = read_efuse_bootrom();
252 armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
253 DEVSPEED_ARMSPEED_SHIFT;
255 return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS);
258 int get_max_dev_speed(void)
260 u32 devspeed = read_efuse_bootrom();
262 devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
263 DEVSPEED_DEVSPEED_SHIFT;
265 return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS);
269 * pll_freq_get - get pll frequency
270 * @pll: pll identifier
272 static unsigned long pll_freq_get(int pll)
274 unsigned long mult = 1, prediv = 1, output_div = 2;
278 if (pll == MAIN_PLL) {
279 ret = external_clk[sys_clk];
280 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) {
282 tmp = __raw_readl(KS2_MAINPLLCTL0);
283 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
284 mult = ((tmp & CFG_PLLCTL0_PLLM_HI_MASK) >>
285 CFG_PLLCTL0_PLLM_SHIFT |
286 (pllctl_reg_read(pll, mult) &
287 PLLM_MULT_LO_MASK)) + 1;
288 output_div = ((pllctl_reg_read(pll, secctl) &
289 SECCTL_OP_DIV_MASK) >>
290 SECCTL_OP_DIV_SHIFT) + 1;
292 ret = ret / prediv / output_div * mult;
297 ret = external_clk[pa_clk];
298 reg = KS2_PASSPLLCTL0;
301 ret = external_clk[tetris_clk];
302 reg = KS2_ARMPLLCTL0;
305 ret = external_clk[ddr3a_clk];
306 reg = KS2_DDR3APLLCTL0;
309 ret = external_clk[ddr3b_clk];
310 reg = KS2_DDR3BPLLCTL0;
316 tmp = __raw_readl(reg);
318 if (!(tmp & CFG_PLLCTL0_BYPASS_MASK)) {
319 /* Bypass disabled */
320 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
321 mult = ((tmp & CFG_PLLCTL0_PLLM_MASK) >>
322 CFG_PLLCTL0_PLLM_SHIFT) + 1;
323 output_div = ((tmp & CFG_PLLCTL0_CLKOD_MASK) >>
324 CFG_PLLCTL0_CLKOD_SHIFT) + 1;
325 ret = ((ret / prediv) * mult) / output_div;
332 unsigned long clk_get_rate(unsigned int clk)
334 unsigned long freq = 0;
338 freq = pll_freq_get(CORE_PLL);
341 freq = pll_freq_get(PASS_PLL);
345 freq = pll_freq_get(TETRIS_PLL);
348 freq = pll_freq_get(DDR3A_PLL);
352 freq = pll_freq_get(DDR3B_PLL);
356 freq = pll_freq_get(CORE_PLL) / pll0div_read(1);
359 return pll_freq_get(CORE_PLL) / pll0div_read(2);
362 freq = pll_freq_get(CORE_PLL) / pll0div_read(3);
365 freq = pll_freq_get(CORE_PLL) / pll0div_read(4);
368 freq = clk_get_rate(sys_clk0_clk) / 2;
371 freq = clk_get_rate(sys_clk0_clk) / 3;
374 freq = clk_get_rate(sys_clk0_clk) / 4;
377 freq = clk_get_rate(sys_clk0_clk) / 6;
380 freq = clk_get_rate(sys_clk0_clk) / 8;
382 case sys_clk0_12_clk:
383 freq = clk_get_rate(sys_clk0_clk) / 12;
385 case sys_clk0_24_clk:
386 freq = clk_get_rate(sys_clk0_clk) / 24;
389 freq = clk_get_rate(sys_clk1_clk) / 3;
392 freq = clk_get_rate(sys_clk1_clk) / 4;
395 freq = clk_get_rate(sys_clk1_clk) / 6;
397 case sys_clk1_12_clk:
398 freq = clk_get_rate(sys_clk1_clk) / 12;