2 * Keystone2: pll initialization
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/clock_defs.h>
16 static void wait_for_completion(const struct pll_init_data *data)
19 for (i = 0; i < 100; i++) {
21 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK))
26 static inline void bypass_main_pll(const struct pll_init_data *data)
28 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK |
31 /* 4 cycles of reference clock CLKIN*/
35 static void configure_mult_div(const struct pll_init_data *data)
37 u32 pllm, plld, bwadj;
39 pllm = data->pll_m - 1;
40 plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;
42 /* Program Multiplier */
43 if (data->pll == MAIN_PLL)
44 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
46 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
47 CFG_PLLCTL0_PLLM_MASK,
48 pllm << CFG_PLLCTL0_PLLM_SHIFT);
51 bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */
52 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
53 CFG_PLLCTL0_BWADJ_MASK,
54 (bwadj << CFG_PLLCTL0_BWADJ_SHIFT) &
55 CFG_PLLCTL0_BWADJ_MASK);
56 bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS;
57 clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
58 CFG_PLLCTL1_BWADJ_MASK, bwadj);
61 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
62 CFG_PLLCTL0_PLLD_MASK, plld);
65 void configure_main_pll(const struct pll_init_data *data)
67 u32 tmp, pllod, i, alnctl_val = 0;
70 pllod = data->pll_od - 1;
72 /* 100 micro sec for stabilization */
75 tmp = pllctl_reg_read(data->pll, secctl);
77 /* Check for Bypass */
78 if (tmp & SECCTL_BYPASS_MASK) {
79 setbits_le32(keystone_pll_regs[data->pll].reg1,
80 CFG_PLLCTL1_ENSAT_MASK);
82 bypass_main_pll(data);
84 /* Powerdown and powerup Main Pll */
85 pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK);
86 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
90 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
92 bypass_main_pll(data);
95 configure_mult_div(data);
97 /* Program Output Divider */
98 pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK,
99 ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK));
101 /* Program PLLDIVn */
102 wait_for_completion(data);
103 for (i = 0; i < PLLDIV_MAX; i++) {
105 offset = pllctl_reg(data->pll, div1) + i;
107 offset = pllctl_reg(data->pll, div4) + (i - 3);
109 if (divn_val[i] != -1) {
110 __raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset);
111 alnctl_val |= BIT(i);
116 pllctl_reg_setbits(data->pll, alnctl, alnctl_val);
118 * Set GOSET bit in PLLCMD to initiate the GO operation
119 * to change the divide
121 pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK);
122 wait_for_completion(data);
126 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
127 sdelay(21000); /* Wait for a minimum of 7 us*/
128 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
129 sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
132 pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK);
133 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK);
136 void configure_secondary_pll(const struct pll_init_data *data)
138 int pllod = data->pll_od - 1;
140 /* Enable Bypass mode */
141 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
142 setbits_le32(keystone_pll_regs[data->pll].reg0,
143 CFG_PLLCTL0_BYPASS_MASK);
145 /* Enable Glitch free bypass for ARM PLL */
146 if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
147 clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
149 configure_mult_div(data);
151 /* Program Output Divider */
152 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
153 CFG_PLLCTL0_CLKOD_MASK,
154 (pllod << CFG_PLLCTL0_CLKOD_SHIFT) &
155 CFG_PLLCTL0_CLKOD_MASK);
158 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
159 /* Wait for 5 micro seconds */
162 /* Select the Output of PASS PLL as input to PASS */
163 if (data->pll == PASS_PLL)
164 setbits_le32(keystone_pll_regs[data->pll].reg1,
165 CFG_PLLCTL1_PAPLL_MASK);
167 /* Select the Output of ARM PLL as input to ARM */
168 if (data->pll == TETRIS_PLL)
169 setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
171 clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
172 /* Wait for 500 * REFCLK cucles * (PLLD + 1) */
175 /* Switch to PLL mode */
176 clrbits_le32(keystone_pll_regs[data->pll].reg0,
177 CFG_PLLCTL0_BYPASS_MASK);
180 void init_pll(const struct pll_init_data *data)
182 if (data->pll == MAIN_PLL)
183 configure_main_pll(data);
185 configure_secondary_pll(data);
188 * This is required to provide a delay between multiple
189 * consequent PPL configurations
194 void init_plls(int num_pll, struct pll_init_data *config)
198 for (i = 0; i < num_pll; i++)
199 init_pll(&config[i]);
202 static int get_max_speed(u32 val, int *speeds)
209 for (j = 1; j < MAX_SPEEDS; j++) {
218 #ifdef CONFIG_SOC_K2HK
219 static u32 read_efuse_bootrom(void)
221 return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
222 __raw_readl(KS2_REV1_DEVSPEED);
225 static inline u32 read_efuse_bootrom(void)
227 return __raw_readl(KS2_EFUSE_BOOTROM);
231 #ifndef CONFIG_SOC_K2E
232 inline int get_max_arm_speed(void)
234 return get_max_speed(read_efuse_bootrom() & 0xffff, arm_speeds);
238 inline int get_max_dev_speed(void)
240 return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds);