2 * Keystone2: pll initialization
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/clock_defs.h>
14 /* DEV and ARM speed definitions as specified in DEVSPEED register */
15 int __weak speeds[DEVSPEED_NUMSPDS] = {
28 const struct keystone_pll_regs keystone_pll_regs[] = {
29 [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
30 [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
31 [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
32 [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
33 [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
34 [UART_PLL] = {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1},
37 inline void pll_pa_clk_sel(void)
39 setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK);
42 static void wait_for_completion(const struct pll_init_data *data)
45 for (i = 0; i < 100; i++) {
47 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK))
52 static inline void bypass_main_pll(const struct pll_init_data *data)
54 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK |
57 /* 4 cycles of reference clock CLKIN*/
61 static void configure_mult_div(const struct pll_init_data *data)
63 u32 pllm, plld, bwadj;
65 pllm = data->pll_m - 1;
66 plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;
68 /* Program Multiplier */
69 if (data->pll == MAIN_PLL)
70 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
72 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
73 CFG_PLLCTL0_PLLM_MASK,
74 pllm << CFG_PLLCTL0_PLLM_SHIFT);
77 bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */
78 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
79 CFG_PLLCTL0_BWADJ_MASK,
80 (bwadj << CFG_PLLCTL0_BWADJ_SHIFT) &
81 CFG_PLLCTL0_BWADJ_MASK);
82 bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS;
83 clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
84 CFG_PLLCTL1_BWADJ_MASK, bwadj);
87 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
88 CFG_PLLCTL0_PLLD_MASK, plld);
91 void configure_main_pll(const struct pll_init_data *data)
93 u32 tmp, pllod, i, alnctl_val = 0;
96 pllod = data->pll_od - 1;
98 /* 100 micro sec for stabilization */
101 tmp = pllctl_reg_read(data->pll, secctl);
103 /* Check for Bypass */
104 if (tmp & SECCTL_BYPASS_MASK) {
105 setbits_le32(keystone_pll_regs[data->pll].reg1,
106 CFG_PLLCTL1_ENSAT_MASK);
108 bypass_main_pll(data);
110 /* Powerdown and powerup Main Pll */
111 pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK);
112 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
116 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
118 bypass_main_pll(data);
121 configure_mult_div(data);
123 /* Program Output Divider */
124 pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK,
125 ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK));
127 /* Program PLLDIVn */
128 wait_for_completion(data);
129 for (i = 0; i < PLLDIV_MAX; i++) {
131 offset = pllctl_reg(data->pll, div1) + i;
133 offset = pllctl_reg(data->pll, div4) + (i - 3);
135 if (divn_val[i] != -1) {
136 __raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset);
137 alnctl_val |= BIT(i);
142 pllctl_reg_setbits(data->pll, alnctl, alnctl_val);
144 * Set GOSET bit in PLLCMD to initiate the GO operation
145 * to change the divide
147 pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK);
148 wait_for_completion(data);
152 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
153 sdelay(21000); /* Wait for a minimum of 7 us*/
154 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
155 sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
158 pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK);
159 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK);
162 void configure_secondary_pll(const struct pll_init_data *data)
164 int pllod = data->pll_od - 1;
166 /* Enable Bypass mode */
167 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
168 setbits_le32(keystone_pll_regs[data->pll].reg0,
169 CFG_PLLCTL0_BYPASS_MASK);
171 /* Enable Glitch free bypass for ARM PLL */
172 if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
173 clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
175 configure_mult_div(data);
177 /* Program Output Divider */
178 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
179 CFG_PLLCTL0_CLKOD_MASK,
180 (pllod << CFG_PLLCTL0_CLKOD_SHIFT) &
181 CFG_PLLCTL0_CLKOD_MASK);
184 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
185 /* Wait for 5 micro seconds */
188 /* Select the Output of PASS PLL as input to PASS */
189 if (data->pll == PASS_PLL && cpu_is_k2hk())
192 /* Select the Output of ARM PLL as input to ARM */
193 if (data->pll == TETRIS_PLL)
194 setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
196 clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
197 /* Wait for 500 * REFCLK cucles * (PLLD + 1) */
200 /* Switch to PLL mode */
201 clrbits_le32(keystone_pll_regs[data->pll].reg0,
202 CFG_PLLCTL0_BYPASS_MASK);
205 void init_pll(const struct pll_init_data *data)
207 if (data->pll == MAIN_PLL)
208 configure_main_pll(data);
210 configure_secondary_pll(data);
213 * This is required to provide a delay between multiple
214 * consequent PPL configurations
221 struct pll_init_data *data;
224 for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {
225 data = get_pll_init_data(pll);
231 static int get_max_speed(u32 val, u32 speed_supported)
235 /* Left most setbit gives the speed */
236 for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {
237 if ((val & BIT(speed)) & speed_supported)
238 return speeds[speed];
241 /* If no bit is set, use SPD800 */
245 static inline u32 read_efuse_bootrom(void)
247 if (cpu_is_k2hk() && (cpu_revision() <= 1))
248 return __raw_readl(KS2_REV1_DEVSPEED);
250 return __raw_readl(KS2_EFUSE_BOOTROM);
253 int get_max_arm_speed(void)
255 u32 armspeed = read_efuse_bootrom();
257 armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
258 DEVSPEED_ARMSPEED_SHIFT;
260 return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS);
263 int get_max_dev_speed(void)
265 u32 devspeed = read_efuse_bootrom();
267 devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
268 DEVSPEED_DEVSPEED_SHIFT;
270 return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS);
274 * pll_freq_get - get pll frequency
275 * @pll: pll identifier
277 static unsigned long pll_freq_get(int pll)
279 unsigned long mult = 1, prediv = 1, output_div = 2;
283 if (pll == MAIN_PLL) {
284 ret = external_clk[sys_clk];
285 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) {
287 tmp = __raw_readl(KS2_MAINPLLCTL0);
288 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
289 mult = ((tmp & CFG_PLLCTL0_PLLM_HI_MASK) >>
290 CFG_PLLCTL0_PLLM_SHIFT |
291 (pllctl_reg_read(pll, mult) &
292 PLLM_MULT_LO_MASK)) + 1;
293 output_div = ((pllctl_reg_read(pll, secctl) &
294 SECCTL_OP_DIV_MASK) >>
295 SECCTL_OP_DIV_SHIFT) + 1;
297 ret = ret / prediv / output_div * mult;
302 ret = external_clk[pa_clk];
303 reg = KS2_PASSPLLCTL0;
306 ret = external_clk[tetris_clk];
307 reg = KS2_ARMPLLCTL0;
310 ret = external_clk[ddr3a_clk];
311 reg = KS2_DDR3APLLCTL0;
314 ret = external_clk[ddr3b_clk];
315 reg = KS2_DDR3BPLLCTL0;
318 ret = external_clk[uart_clk];
319 reg = KS2_UARTPLLCTL0;
325 tmp = __raw_readl(reg);
327 if (!(tmp & CFG_PLLCTL0_BYPASS_MASK)) {
328 /* Bypass disabled */
329 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
330 mult = ((tmp & CFG_PLLCTL0_PLLM_MASK) >>
331 CFG_PLLCTL0_PLLM_SHIFT) + 1;
332 output_div = ((tmp & CFG_PLLCTL0_CLKOD_MASK) >>
333 CFG_PLLCTL0_CLKOD_SHIFT) + 1;
334 ret = ((ret / prediv) * mult) / output_div;
341 unsigned long clk_get_rate(unsigned int clk)
343 unsigned long freq = 0;
347 freq = pll_freq_get(CORE_PLL);
350 freq = pll_freq_get(PASS_PLL);
354 freq = pll_freq_get(TETRIS_PLL);
357 freq = pll_freq_get(DDR3A_PLL);
361 freq = pll_freq_get(DDR3B_PLL);
365 freq = pll_freq_get(UART_PLL);
369 freq = pll_freq_get(CORE_PLL) / pll0div_read(1);
372 return pll_freq_get(CORE_PLL) / pll0div_read(2);
375 freq = pll_freq_get(CORE_PLL) / pll0div_read(3);
378 freq = pll_freq_get(CORE_PLL) / pll0div_read(4);
381 freq = clk_get_rate(sys_clk0_clk) / 2;
384 freq = clk_get_rate(sys_clk0_clk) / 3;
387 freq = clk_get_rate(sys_clk0_clk) / 4;
390 freq = clk_get_rate(sys_clk0_clk) / 6;
393 freq = clk_get_rate(sys_clk0_clk) / 8;
395 case sys_clk0_12_clk:
396 freq = clk_get_rate(sys_clk0_clk) / 12;
398 case sys_clk0_24_clk:
399 freq = clk_get_rate(sys_clk0_clk) / 24;
402 freq = clk_get_rate(sys_clk1_clk) / 3;
405 freq = clk_get_rate(sys_clk1_clk) / 4;
408 freq = clk_get_rate(sys_clk1_clk) / 6;
410 case sys_clk1_12_clk:
411 freq = clk_get_rate(sys_clk1_clk) / 12;