git.sur5r.net Git - u-boot/blob - arch/arm/mach-keystone/ddr3.c

   1 /*
   2  * Keystone2: DDR3 initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <asm/io.h>
  11 #include <common.h>
  12 #include <asm/arch/msmc.h>
  13 #include <asm/arch/ddr3.h>
  14 #include <asm/arch/psc_defs.h>
  15
  16 #include <asm/ti-common/ti-edma3.h>
  17
  18 #define DDR3_EDMA_BLK_SIZE_SHIFT        10
  19 #define DDR3_EDMA_BLK_SIZE              (1 << DDR3_EDMA_BLK_SIZE_SHIFT)
  20 #define DDR3_EDMA_BCNT                  0x8000
  21 #define DDR3_EDMA_CCNT                  1
  22 #define DDR3_EDMA_XF_SIZE               (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
  23 #define DDR3_EDMA_SLOT_NUM              1
  24
  25 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
  26 {
  27         unsigned int tmp;
  28
  29         while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
  30                  & 0x00000001) != 0x00000001)
  31                 ;
  32
  33         __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
  34
  35         tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
  36         tmp &= ~(phy_cfg->pgcr1_mask);
  37         tmp |= phy_cfg->pgcr1_val;
  38         __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
  39
  40         __raw_writel(phy_cfg->ptr0,   base + KS2_DDRPHY_PTR0_OFFSET);
  41         __raw_writel(phy_cfg->ptr1,   base + KS2_DDRPHY_PTR1_OFFSET);
  42         __raw_writel(phy_cfg->ptr3,  base + KS2_DDRPHY_PTR3_OFFSET);
  43         __raw_writel(phy_cfg->ptr4,  base + KS2_DDRPHY_PTR4_OFFSET);
  44
  45         tmp =  __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
  46         tmp &= ~(phy_cfg->dcr_mask);
  47         tmp |= phy_cfg->dcr_val;
  48         __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
  49
  50         __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
  51         __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
  52         __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
  53         __raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
  54         __raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
  55         if (!cpu_is_k2g())
  56                 __raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
  57         __raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
  58         __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
  59
  60         __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
  61         __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
  62         __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
  63
  64         __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
  65         while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  66                 ;
  67
  68         if (cpu_is_k2g()) {
  69                 setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
  70                 clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
  71                 clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
  72                 clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
  73                 clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
  74         }
  75
  76         __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
  77         while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  78                 ;
  79 }
  80
  81 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
  82 {
  83         __raw_writel(emif_cfg->sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);
  84         __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
  85         __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
  86         __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
  87         __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
  88         __raw_writel(emif_cfg->zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);
  89         __raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
  90 }
  91
  92 int ddr3_ecc_support_rmw(u32 base)
  93 {
  94         u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
  95
  96         /* Check the DDR3 controller ID reg if the controllers
  97            supports ECC RMW or not */
  98         if (value == 0x40461C02)
  99                 return 1;
 100
 101         return 0;
 102 }
 103
 104 static void ddr3_ecc_config(u32 base, u32 value)
 105 {
 106         u32 data;
 107
 108         __raw_writel(value,  base + KS2_DDR3_ECC_CTRL_OFFSET);
 109         udelay(100000); /* delay required to synchronize across clock domains */
 110
 111         if (value & KS2_DDR3_ECC_EN) {
 112                 /* Clear the 1-bit error count */
 113                 data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
 114                 __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
 115
 116                 /* enable the ECC interrupt */
 117                 __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
 118                              KS2_DDR3_WR_ECC_ERR_SYS,
 119                              base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
 120
 121                 /* Clear the ECC error interrupt status */
 122                 __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
 123                              KS2_DDR3_WR_ECC_ERR_SYS,
 124                              base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
 125         }
 126 }
 127
 128 static void ddr3_reset_data(u32 base, u32 ddr3_size)
 129 {
 130         u32 mpax[2];
 131         u32 seg_num;
 132         u32 seg, blks, dst, edma_blks;
 133         struct edma3_slot_config slot;
 134         struct edma3_channel_config edma_channel;
 135         u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
 136
 137         /* Setup an edma to copy the 1k block to the entire DDR */
 138         puts("\nClear entire DDR3 memory to enable ECC\n");
 139
 140         /* save the SES MPAX regs */
 141         if (cpu_is_k2g())
 142                 msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
 143         else
 144                 msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
 145
 146         /* setup edma slot 1 configuration */
 147         slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
 148                    EDMA3_SLOPT_COMP_CODE(0) |
 149                    EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
 150         slot.bcnt = DDR3_EDMA_BCNT;
 151         slot.acnt = DDR3_EDMA_BLK_SIZE;
 152         slot.ccnt = DDR3_EDMA_CCNT;
 153         slot.src_bidx = 0;
 154         slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
 155         slot.src_cidx = 0;
 156         slot.dst_cidx = 0;
 157         slot.link = EDMA3_PARSET_NULL_LINK;
 158         slot.bcntrld = 0;
 159         edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
 160
 161         /* configure quik edma channel */
 162         edma_channel.slot = DDR3_EDMA_SLOT_NUM;
 163         edma_channel.chnum = 0;
 164         edma_channel.complete_code = 0;
 165         /* event trigger after dst update */
 166         edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
 167         qedma3_start(KS2_EDMA0_BASE, &edma_channel);
 168
 169         /* DDR3 size in segments (4KB seg size) */
 170         seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
 171
 172         for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
 173                 /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
 174                    access slave interface so that edma driver can access */
 175                 if (cpu_is_k2g()) {
 176                         msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
 177                                              base >> KS2_MSMC_SEG_SIZE_SHIFT,
 178                                              KS2_MSMC_DST_SEG_BASE + seg,
 179                                              MPAX_SEG_2G);
 180                 } else {
 181                         msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0,
 182                                              base >> KS2_MSMC_SEG_SIZE_SHIFT,
 183                                              KS2_MSMC_DST_SEG_BASE + seg,
 184                                              MPAX_SEG_2G);
 185                 }
 186
 187                 if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
 188                         edma_blks = KS2_MSMC_MAP_SEG_NUM <<
 189                                         (KS2_MSMC_SEG_SIZE_SHIFT
 190                                         - DDR3_EDMA_BLK_SIZE_SHIFT);
 191                 else
 192                         edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
 193                                         - DDR3_EDMA_BLK_SIZE_SHIFT);
 194
 195                 /* Use edma driver to scrub 2GB DDR memory */
 196                 for (dst = base, blks = 0; blks < edma_blks;
 197                      blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
 198                         edma3_set_src_addr(KS2_EDMA0_BASE,
 199                                            edma_channel.slot, (u32)edma_src);
 200                         edma3_set_dest_addr(KS2_EDMA0_BASE,
 201                                             edma_channel.slot, (u32)dst);
 202
 203                         while (edma3_check_for_transfer(KS2_EDMA0_BASE,
 204                                                         &edma_channel))
 205                                 udelay(10);
 206                 }
 207         }
 208
 209         qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
 210
 211         /* restore the SES MPAX regs */
 212         if (cpu_is_k2g())
 213                 msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
 214         else
 215                 msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
 216 }
 217
 218 static void ddr3_ecc_init_range(u32 base)
 219 {
 220         u32 ecc_val = KS2_DDR3_ECC_EN;
 221         u32 rmw = ddr3_ecc_support_rmw(base);
 222
 223         if (rmw)
 224                 ecc_val |= KS2_DDR3_ECC_RMW_EN;
 225
 226         __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
 227
 228         ddr3_ecc_config(base, ecc_val);
 229 }
 230
 231 void ddr3_enable_ecc(u32 base, int test)
 232 {
 233         u32 ecc_val = KS2_DDR3_ECC_ENABLE;
 234         u32 rmw = ddr3_ecc_support_rmw(base);
 235
 236         if (test)
 237                 ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
 238
 239         if (!rmw) {
 240                 if (!test)
 241                         /* by default, disable ecc when rmw = 0 and no
 242                            ecc test */
 243                         ecc_val = 0;
 244         } else {
 245                 ecc_val |= KS2_DDR3_ECC_RMW_EN;
 246         }
 247
 248         ddr3_ecc_config(base, ecc_val);
 249 }
 250
 251 void ddr3_disable_ecc(u32 base)
 252 {
 253         ddr3_ecc_config(base, 0);
 254 }
 255
 256 #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
 257 static void cic_init(u32 base)
 258 {
 259         /* Disable CIC global interrupts */
 260         __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
 261
 262         /* Set to normal mode, no nesting, no priority hold */
 263         __raw_writel(0, base + KS2_CIC_CTRL);
 264         __raw_writel(0, base + KS2_CIC_HOST_CTRL);
 265
 266         /* Enable CIC global interrupts */
 267         __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
 268 }
 269
 270 static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
 271 {
 272         /* Map the system interrupt to a CIC channel */
 273         __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
 274
 275         /* Enable CIC system interrupt */
 276         __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
 277
 278         /* Enable CIC Host interrupt */
 279         __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
 280 }
 281
 282 static void ddr3_map_ecc_cic2_irq(u32 base)
 283 {
 284         cic_init(base);
 285         cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
 286                            KS2_CIC2_DDR3_ECC_IRQ_NUM);
 287 }
 288 #endif
 289
 290 void ddr3_init_ecc(u32 base, u32 ddr3_size)
 291 {
 292         if (!ddr3_ecc_support_rmw(base)) {
 293                 ddr3_disable_ecc(base);
 294                 return;
 295         }
 296
 297         ddr3_ecc_init_range(base);
 298         ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
 299
 300         /* mapping DDR3 ECC system interrupt from CIC2 to GIC */
 301 #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
 302         ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
 303 #endif
 304         ddr3_enable_ecc(base, 0);
 305 }
 306
 307 void ddr3_check_ecc_int(u32 base)
 308 {
 309         char *env;
 310         int ecc_test = 0;
 311         u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
 312
 313         env = getenv("ecc_test");
 314         if (env)
 315                 ecc_test = simple_strtol(env, NULL, 0);
 316
 317         if (value & KS2_DDR3_WR_ECC_ERR_SYS)
 318                 puts("DDR3 ECC write error interrupted\n");
 319
 320         if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
 321                 puts("DDR3 ECC 2-bit error interrupted\n");
 322
 323                 if (!ecc_test) {
 324                         puts("Reseting the device ...\n");
 325                         reset_cpu(0);
 326                 }
 327         }
 328
 329         value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
 330         if (value) {
 331                 printf("1-bit ECC err count: 0x%x\n", value);
 332                 value = __raw_readl(base +
 333                                     KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
 334                 printf("1-bit ECC err address log: 0x%x\n", value);
 335         }
 336 }
 337
 338 void ddr3_reset_ddrphy(void)
 339 {
 340         u32 tmp;
 341
 342         /* Assert DDR3A  PHY reset */
 343         tmp = readl(KS2_DDR3APLLCTL1);
 344         tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
 345         writel(tmp, KS2_DDR3APLLCTL1);
 346
 347         /* wait 10us to catch the reset */
 348         udelay(10);
 349
 350         /* Release DDR3A PHY reset */
 351         tmp = readl(KS2_DDR3APLLCTL1);
 352         tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
 353         __raw_writel(tmp, KS2_DDR3APLLCTL1);
 354 }
 355
 356 #ifdef CONFIG_SOC_K2HK
 357 /**
 358  * ddr3_reset_workaround - reset workaround in case if leveling error
 359  * detected for PG 1.0 and 1.1 k2hk SoCs
 360  */
 361 void ddr3_err_reset_workaround(void)
 362 {
 363         unsigned int tmp;
 364         unsigned int tmp_a;
 365         unsigned int tmp_b;
 366
 367         /*
 368          * Check for PGSR0 error bits of DDR3 PHY.
 369          * Check for WLERR, QSGERR, WLAERR,
 370          * RDERR, WDERR, REERR, WEERR error to see if they are set or not
 371          */
 372         tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
 373         tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
 374
 375         if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
 376                 printf("DDR Leveling Error Detected!\n");
 377                 printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
 378                 printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
 379
 380                 /*
 381                  * Write Keys to KICK registers to enable writes to registers
 382                  * in boot config space
 383                  */
 384                 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
 385                 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
 386
 387                 /*
 388                  * Move DDR3A Module out of reset isolation by setting
 389                  * MDCTL23[12] = 0
 390                  */
 391                 tmp_a = __raw_readl(KS2_PSC_BASE +
 392                                     PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
 393
 394                 tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
 395                 __raw_writel(tmp_a, KS2_PSC_BASE +
 396                              PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
 397
 398                 /*
 399                  * Move DDR3B Module out of reset isolation by setting
 400                  * MDCTL24[12] = 0
 401                  */
 402                 tmp_b = __raw_readl(KS2_PSC_BASE +
 403                                     PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
 404                 tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
 405                 __raw_writel(tmp_b, KS2_PSC_BASE +
 406                              PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
 407
 408                 /*
 409                  * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
 410                  * to RSTCTRL and RSTCFG
 411                  */
 412                 tmp = __raw_readl(KS2_RSTCTRL);
 413                 tmp &= KS2_RSTCTRL_MASK;
 414                 tmp |= KS2_RSTCTRL_KEY;
 415                 __raw_writel(tmp, KS2_RSTCTRL);
 416
 417                 /*
 418                  * Set PLL Controller to drive hard reset on SW trigger by
 419                  * setting RSTCFG[13] = 0
 420                  */
 421                 tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
 422                 tmp &= ~KS2_RSTYPE_PLL_SOFT;
 423                 __raw_writel(tmp, KS2_RSTCTRL_RSCFG);
 424
 425                 reset_cpu(0);
 426         }
 427 }
 428 #endif