1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * K2E: Clock management APIs
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
9 #ifndef __ASM_ARCH_CLOCK_K2E_H
10 #define __ASM_ARCH_CLOCK_K2E_H
12 #define PLLSET_CMD_LIST "<pa|ddr3>"
14 #define KS2_CLK1_6 sys_clk0_6_clk
16 #define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
17 #define CORE_PLL_850 {CORE_PLL, 17, 1, 2}
18 #define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
19 #define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
20 #define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
21 #define CORE_PLL_1250 {CORE_PLL, 25, 1, 2}
22 #define CORE_PLL_1350 {CORE_PLL, 27, 1, 2}
23 #define CORE_PLL_1400 {CORE_PLL, 28, 1, 2}
24 #define CORE_PLL_1500 {CORE_PLL, 30, 1, 2}
25 #define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
26 #define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
27 #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
28 #define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
30 /* k2e DEV supports 800, 850, 1000, 1250, 1350, 1400, 1500 MHz */
31 #define DEV_SUPPORTED_SPEEDS 0xFFF
32 #define ARM_SUPPORTED_SPEEDS 0