2 * keystone2: common pll clock definitions
3 * (C) Copyright 2012-2014
4 * Texas Instruments Incorporated, <www.ti.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #define _CLOCK_DEFS_H_
12 #include <asm/arch/hardware.h>
14 #define BIT(x) (1 << (x))
16 /* PLL Control Registers */
52 static struct pllctl_regs *pllctl_regs[] = {
53 (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
56 #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
57 #define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
58 #define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
60 #define pllctl_reg_rmw(pll, reg, mask, val) \
61 pllctl_reg_write(pll, reg, \
62 (pllctl_reg_read(pll, reg) & ~(mask)) | val)
64 #define pllctl_reg_setbits(pll, reg, mask) \
65 pllctl_reg_rmw(pll, reg, 0, mask)
67 #define pllctl_reg_clrbits(pll, reg, mask) \
68 pllctl_reg_rmw(pll, reg, mask, 0)
70 #define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
72 #define PLLCTL_BYPASS BIT(23)
73 #define PLL_PLLRST BIT(14)
74 #define PLLCTL_PAPLL BIT(13)
75 #define PLLCTL_CLKMODE BIT(8)
76 #define PLLCTL_PLLSELB BIT(7)
77 #define PLLCTL_ENSAT BIT(6)
78 #define PLLCTL_PLLENSRC BIT(5)
79 #define PLLCTL_PLLDIS BIT(4)
80 #define PLLCTL_PLLRST BIT(3)
81 #define PLLCTL_PLLPWRDN BIT(1)
82 #define PLLCTL_PLLEN BIT(0)
83 #define PLLSTAT_GO BIT(0)
85 #define MAIN_ENSAT_OFFSET 6
87 #define PLLDIV_ENABLE BIT(15)
89 #define PLL_DIV_MASK 0x3f
90 #define PLL_MULT_MASK 0x1fff
91 #define PLL_MULT_SHIFT 6
92 #define PLLM_MULT_HI_MASK 0x7f
93 #define PLLM_MULT_HI_SHIFT 12
94 #define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
95 #define PLLM_MULT_LO_MASK 0x3f
96 #define PLL_CLKOD_MASK 0xf
97 #define PLL_CLKOD_SHIFT 19
98 #define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
99 #define PLL_BWADJ_LO_MASK 0xff
100 #define PLL_BWADJ_LO_SHIFT 24
101 #define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
102 #define PLL_BWADJ_HI_MASK 0xf
105 #define PLLCTL_PLLENSRC_SHIF 5
106 #define PLLCTL_PLLENSRC_MASK BIT(5)
107 #define PLLCTL_PLLRST_SHIFT 3
108 #define PLLCTL_PLLRST_MASK BIT(3)
109 #define PLLCTL_PLLPWRDN_SHIFT 1
110 #define PLLCTL_PLLPWRDN_MASK BIT(1)
111 #define PLLCTL_PLLEN_SHIFT 0
112 #define PLLCTL_PLLEN_MASK BIT(0)
115 #define SECCTL_BYPASS_SHIFT 23
116 #define SECCTL_BYPASS_MASK BIT(23)
117 #define SECCTL_OP_DIV_SHIFT 19
118 #define SECCTL_OP_DIV_MASK (0xf << 19)
121 #define PLLM_MULT_LO_SHIFT 0
122 #define PLLM_MULT_LO_MASK 0x3f
123 #define PLLM_MULT_LO_BITS 6
126 #define PLLDIV_ENABLE_SHIFT 15
127 #define PLLDIV_ENABLE_MASK BIT(15)
128 #define PLLDIV_RATIO_SHIFT 0x0
129 #define PLLDIV_RATIO_MASK 0xff
130 #define PLLDIV_MAX 16
133 #define PLLCMD_GOSET_SHIFT 0
134 #define PLLCMD_GOSET_MASK BIT(0)
137 #define PLLSTAT_GOSTAT_SHIFT 0
138 #define PLLSTAT_GOSTAT_MASK BIT(0)
140 /* Device Config PLLCTL0 */
141 #define CFG_PLLCTL0_BWADJ_SHIFT 24
142 #define CFG_PLLCTL0_BWADJ_MASK (0xff << 24)
143 #define CFG_PLLCTL0_BWADJ_BITS 8
144 #define CFG_PLLCTL0_BYPASS_SHIFT 23
145 #define CFG_PLLCTL0_BYPASS_MASK BIT(23)
146 #define CFG_PLLCTL0_CLKOD_SHIFT 19
147 #define CFG_PLLCTL0_CLKOD_MASK (0xf << 19)
148 #define CFG_PLLCTL0_PLLM_HI_SHIFT 12
149 #define CFG_PLLCTL0_PLLM_HI_MASK (0x7f << 12)
150 #define CFG_PLLCTL0_PLLM_SHIFT 6
151 #define CFG_PLLCTL0_PLLM_MASK (0x1fff << 6)
152 #define CFG_PLLCTL0_PLLD_SHIFT 0
153 #define CFG_PLLCTL0_PLLD_MASK 0x3f
155 /* Device Config PLLCTL1 */
156 #define CFG_PLLCTL1_RST_SHIFT 14
157 #define CFG_PLLCTL1_RST_MASK BIT(14)
158 #define CFG_PLLCTL1_PAPLL_SHIFT 13
159 #define CFG_PLLCTL1_PAPLL_MASK BIT(13)
160 #define CFG_PLLCTL1_ENSAT_SHIFT 6
161 #define CFG_PLLCTL1_ENSAT_MASK BIT(6)
162 #define CFG_PLLCTL1_BWADJ_SHIFT 0
163 #define CFG_PLLCTL1_BWADJ_MASK 0xf
165 #define MISC_CTL1_ARM_PLL_EN BIT(13)
167 #endif /* _CLOCK_DEFS_H_ */