5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/hardware.h>
15 struct ddr3_phy_config {
17 unsigned int pgcr1_mask;
18 unsigned int pgcr1_val;
24 unsigned int dcr_mask;
38 unsigned int datx8_2_mask;
39 unsigned int datx8_2_val;
40 unsigned int datx8_3_mask;
41 unsigned int datx8_3_val;
42 unsigned int datx8_4_mask;
43 unsigned int datx8_4_val;
44 unsigned int datx8_5_mask;
45 unsigned int datx8_5_val;
46 unsigned int datx8_6_mask;
47 unsigned int datx8_6_val;
48 unsigned int datx8_7_mask;
49 unsigned int datx8_7_val;
50 unsigned int datx8_8_mask;
51 unsigned int datx8_8_val;
55 struct ddr3_emif_config {
67 struct ddr3_phy_config phy_cfg;
68 struct ddr3_emif_config emif_cfg;
69 unsigned int ddrspdclock;
74 void ddr3_reset_ddrphy(void);
75 void ddr3_init_ecc(u32 base, u32 ddr3_size);
76 void ddr3_disable_ecc(u32 base);
77 void ddr3_check_ecc_int(u32 base);
78 int ddr3_ecc_support_rmw(u32 base);
79 void ddr3_err_reset_workaround(void);
80 void ddr3_enable_ecc(u32 base, int test);
81 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
82 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
83 int ddr3_get_size(void);