1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Texas Instruments Incorporated, <www.ti.com>
12 #include <asm/arch/hardware.h>
14 struct ddr3_phy_config {
16 unsigned int pgcr1_mask;
17 unsigned int pgcr1_val;
23 unsigned int dcr_mask;
37 unsigned int datx8_2_mask;
38 unsigned int datx8_2_val;
39 unsigned int datx8_3_mask;
40 unsigned int datx8_3_val;
41 unsigned int datx8_4_mask;
42 unsigned int datx8_4_val;
43 unsigned int datx8_5_mask;
44 unsigned int datx8_5_val;
45 unsigned int datx8_6_mask;
46 unsigned int datx8_6_val;
47 unsigned int datx8_7_mask;
48 unsigned int datx8_7_val;
49 unsigned int datx8_8_mask;
50 unsigned int datx8_8_val;
54 struct ddr3_emif_config {
66 struct ddr3_phy_config phy_cfg;
67 struct ddr3_emif_config emif_cfg;
68 unsigned int ddrspdclock;
73 void ddr3_reset_ddrphy(void);
74 void ddr3_init_ecc(u32 base, u32 ddr3_size);
75 void ddr3_disable_ecc(u32 base);
76 void ddr3_check_ecc_int(u32 base);
77 int ddr3_ecc_support_rmw(u32 base);
78 void ddr3_err_reset_workaround(void);
79 void ddr3_enable_ecc(u32 base, int test);
80 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
81 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
82 int ddr3_get_size(void);